adithyasunil26
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homebrew-cask Public
Forked from Homebrew/homebrew-cask🍻 A CLI workflow for the administration of macOS applications distributed as binaries
Ruby BSD 2-Clause "Simplified" License Updatedon Jul 11, 2024Jul 11, 2024 -
CMOS-Digital-Design Public
Files from CMOS Digital Design Tutorials
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homebrew-cask-bump Public
Python script to run livecheck and bump-cask-pr for new versions of casks
Python Updatedon May 1, 2024Apr 30, 2024 -
riscvy Public
5 stage pipelined RISC-V processor with forwarding, stalling and flushing
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sscs-ose-code-a-chip.github.io Public
Forked from sscs-ose/sscs-ose-code-a-chip.github.ioIEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
Jupyter Notebook Apache License 2.0 Updatedon Apr 15, 2024Apr 15, 2024 -
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2.87GHz-MWG-MPW5 Public
2.87 GHz microwave signal generator in SKY130
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homebrew-formula-bump Public
Python script to run livecheck and bump-formula-pr for new versions of formulas
Python Updatedon Nov 29, 2023Nov 28, 2023 -
OpenFASOC Public
Forked from idea-fasoc/OpenFASOCFully Open Source FASOC generators built on top of open-source EDA tools
Python Apache License 2.0 Updatedon Jun 1, 2023May 31, 2023 -
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ubisoft-laforge-daft-exprt Public
Forked from ubisoft/ubisoft-laforge-daft-exprtPyTorch Implementation of Daft-Exprt: Robust Prosody Transfer Across Speakers for Expressive Speech Synthesis
Python Apache License 2.0 Updatedon Apr 13, 2022Apr 12, 2022 -
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basejump_stl Public
Forked from bespoke-silicon-group/basejump_stlBaseJump STL: A Standard Template Library for SystemVerilog
Verilog Other Updatedon Jan 12, 2022Jan 11, 2022 -
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CMOS-frequency-synthesizer-SKY130 Public
Forked from efabless/caravel_user_project_analog -
Ring_oscillator_sky130 Public
Forked from efabless/caravel_user_projecthttps://caravel-user-project.readthedocs.io
Verilog Apache License 2.0 Updatedon Dec 29, 2021Dec 28, 2021 -
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Fusesoc-Parameter-Sweeper Public
Sweeping parameters for a FuseSoC target
Python Updatedon Dec 16, 2021Dec 16, 2021 -
xschem Public
Forked from StefanSchippers/xschemA schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
C Other Updatedon Dec 10, 2021Dec 10, 2021 -
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CCIoT-Not-A-Helmet Public
IoT system with dashboard for monitoring working conditions in mines and alerting workers in emergencies.
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basejump_stl_alu Public
Core created as a proof of concept for BaseJump STL integration into FuseSoC. Simple ALU with an SRAM generated by bsg_fakeram.
Verilog Updatedon Aug 31, 2021Aug 30, 2021 -
bsg_fakeram_generator Public
FuseSoC generator for BSG fakeram generator
Python Updatedon Aug 31, 2021Aug 30, 2021