abdelazeem201

I may be slow to respond.

Ahmed Abdelazeem abdelazeem201

I may be slow to respond.

I am a Hardware Engineer with a special interest in Physical ASIC Design.

473 followers · 4 following

Synopsys
Dublin, Ireland.
https://abdelazeem201.github.io/
in/ahmed-abdelazeem
@abdelazeem201
https://stackoverflow.com/users/13645979/ahmed-abdelazeem
https://www.slideshare.net/AhmedAbdelazeem28

Achievements

Tcl-Scripting-for-EDA Public

This course explains the basics of Tcl scripting language, which is embedded in almost all EDA tools and can be used to automate many operations in the user environment.

tcl vlsi tcl-scripts tcl-tk asic-design

Tcl 13 5 MIT License Updated Jul 11, 2026
ASIC-Design-Roadmap Public

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

awesome fpga hardware verilog awesome-list

Verilog 540 68 MIT License Updated Jul 18, 2025
Synopsys-RTL-to-GDSII-Flow Public

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Synopsys tools.

Verilog 14 5 Updated Jun 28, 2025
Digital-Filter Public

Digital Filter

fpga dsp matlab vhdl verilog

Verilog Updated Mar 28, 2025
bsg_rocket Public

C Updated Mar 28, 2025
Machine-Learning-based-Domain-Specific-Hardware-Accelerators Public

Domain Specific Hardware Accelerators

1 2 MIT License Updated Nov 11, 2024
ASIC-Implementation-of-Convolutional-Neural-Network-for-Real-Time-Application Public

ASIC Implementation of Convolutional Neural Network for Real-Time Application

Updated Nov 2, 2024
APB-I2S Public

I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word…

asic fpga verilog vcs synopsys apb i2s

Verilog 7 2 MIT License Updated Oct 24, 2024
Systolic-array-implementation-in-RTL-for-TPU Public

IC implementation of Systolic Array for TPU

asic fpga rtl verilog asic-verification asic-design

Verilog 367 38 MIT License Updated Oct 21, 2024
Spiking-Neural-Processor Public

This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where ne…

asic fpga rtl neuromorphic hardware-acceleration fpga-accelerator

Verilog 11 2 MIT License Updated Oct 19, 2024
abdelazeem201 Public

3 Updated Oct 19, 2024
abdelazeem201.github.io Public

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

JavaScript 1 MIT License Updated Oct 9, 2024
skywater130_scl_9T Public

skywater130_scl_9T for Synopsys and Cadence Flow

Verilog 3 MIT License Updated Sep 28, 2024
Resume Public

A one-page, one column resume template in LaTeX that caters particularly to an undergraduate ECE/CSE student.

TeX 6 MIT License Updated Sep 15, 2024
The-Power-of-TCL Public

Tcl 7 4 Updated Jul 20, 2024
asap7_reference_design Public
Forked from Centre-for-Hardware-Security/asap7_reference_design

reference block design for the ASAP7nm library in Cadence Innovus

Verilog Updated Jun 25, 2024
SoC-FPGA Public

System-on-a-Chip Field-Programmable Gate Array (SoC-FPGA)

Verilog 3 1 MIT License Updated May 13, 2024
Cadence-RTL-to-GDSII-Flow Public

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

Verilog 126 28 MIT License Updated Feb 22, 2024
ICC2_scripts Public

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.

tcl soc pnr tcl-extension

Tcl 29 5 MIT License Updated Feb 11, 2024
VID_TIMING_GEN Public

Video Timing Generator

asic fpga verilog soc

Verilog 2 Updated Jan 23, 2024
awesome-palestine Public
Forked from aborazmeh/awesome-palestine

A curated list of Palestine and Palestinian-Israeli conflict resources.

MIT License Updated Jan 7, 2024
verilog-format Public
Forked from ericsonj/verilog-format

Verilog formatter

Java Updated Jan 2, 2024
RTL-to-Gates-Synthesis-using-Synopsys-tools Public

For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, …

Tcl 9 2 GNU General Public License v3.0 Updated Dec 20, 2023
CS250-Laboratory-1 Public

For this assignment, you will become familiar with the VLSI tools you will use throughout this semester, learn how a design “flows” through the toolflow, and practice Verilog coding. Specifically, …

2 Updated Dec 20, 2023
100daysofRTL Public

Every Day I will be uploading an RTL code with Synthesized Design and TB for RISC CPU Design

cpu vhdl verilog systemverilog

VHDL 6 1 MIT License Updated Dec 4, 2023
Design-and-ASIC-Implementation-of-32-Point-FFT-Processor Public

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) h…

asic fpga vhdl rtl verilog synthesis fft

Verilog 51 6 MIT License Updated Dec 3, 2023
open-eda-course Public
Forked from asinghani/open-eda-course

Jupyter Notebook 1 1 Updated Oct 21, 2023
Course Public

Course

Updated Sep 8, 2023
DTMF Public

Design and Implementation of Goertzel Algorithm for DTMF application on ASIC.

asic fpga dtmf vhdl verilog synthesis soc

Verilog 4 1 MIT License Updated Jul 3, 2023
OsvvmLibraries Public
Forked from OSVVM/OsvvmLibraries

Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

Other Updated Jun 24, 2023

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Ahmed Abdelazeem abdelazeem201

Achievements

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Tcl-Scripting-for-EDA Public

ASIC-Design-Roadmap Public

Synopsys-RTL-to-GDSII-Flow Public

Digital-Filter Public

bsg_rocket Public

Machine-Learning-based-Domain-Specific-Hardware-Accelerators Public

ASIC-Implementation-of-Convolutional-Neural-Network-for-Real-Time-Application Public

APB-I2S Public

Systolic-array-implementation-in-RTL-for-TPU Public

Spiking-Neural-Processor Public

abdelazeem201 Public

abdelazeem201.github.io Public

skywater130_scl_9T Public

Resume Public

The-Power-of-TCL Public

asap7_reference_design Public

SoC-FPGA Public

Cadence-RTL-to-GDSII-Flow Public

ICC2_scripts Public

VID_TIMING_GEN Public

awesome-palestine Public

verilog-format Public

RTL-to-Gates-Synthesis-using-Synopsys-tools Public

CS250-Laboratory-1 Public

100daysofRTL Public

Design-and-ASIC-Implementation-of-32-Point-FFT-Processor Public

open-eda-course Public

Course Public

DTMF Public

OsvvmLibraries Public