A fully functional Connect Four game implemented on the Altera DE1-SoC FPGA board using SystemVerilog for EE 271 Digital Circuit and System Design (UW Winter 2025).

This project implements an interactive Connect Four game that runs directly on FPGA hardware. The game features:

• Real-time gameplay with two players
• VGA display output for game rendering
• Key input controls for player moves
• Hardware-based game logic and validation
• LED indicators for game status

• Two-Player Gameplay: Human vs. Human matches on the same FPGA board
• Hardware Implementation: Entirely synthesized for FPGA execution
• VGA Display: Real-time rendering of game board and pieces
• Input Controls: Key-based controls for piece selection and dropping
• Win Detection: Automatic detection of winning conditions (horizontal, vertical, diagonal)
• Game Status Indicators: LED feedback for current player and game state

• Altera DE1-SoC FPGA Development Board
• VGA Monitor with D-sub 15-pin connector
• USB Blaster programmer
• Quartus II or Quartus Prime (version 15.1 or later recommended)
• ModelSim for simulation

├── DE1_SoC.sv              # Top-level module and system integration
├── DE1_SoC.qpf             # Quartus II project file
├── DE1_SoC.qsf             # Quartus II settings file
├── clock_divider.sv        # Clock frequency divider
├── userInput.sv            # Keyboard input handler
├── selection.sv            # Column selection logic
├── dropAnimator.sv         # Piece drop animation controller
├── boardState.sv           # Game board state management
├── validator.sv            # Move validation logic
├── winDetection.sv         # Win condition detection
├── switchPlayer.sv         # Player switching logic
├── winnerDisplay.sv        # Winner announcement logic
├── renderer.sv             # VGA rendering engine
├── LEDDriver.sv            # Status LED controller
├── frame.sv                # Display frame management
├── mux2_1.sv               # 2-to-1 multiplexer
├── mux4_1.sv               # 4-to-1 multiplexer
├── keyOpt.sv               # Key debouncing/optimization
├── LED_test.sv             # LED testing module
├── test.sv                 # Testbench module
└── simulation/             # ModelSim simulation files
    ├── runlab.do           # Main simulation script
    ├── runlab_*.do         # Module-specific simulation scripts
    └── modelsim/           # ModelSim project files

1. Open DE1_SoC.qpf in Quartus II/Prime
2. Compile the project:
   • Tools → Compile Design (or Ctrl+L)
3. Program the device:
   • Tools → Programmer
   • Select your USB Blaster
   • Load output_files/DE1_SoC.sof
   • Click "Start"

quartus_sh -t ProgramTheDE1_SoC.cdf

1. Open ModelSim
2. File → Open Project → select project from simulation/modelsim/
3. Run simulation scripts:

   do runlab.do                 # Main system simulation
   do runlab_keyop.do          # Keyboard input simulation
   do runlab_bdst.do           # Board state simulation
   do runlab_dropanim.do       # Drop animation simulation
   do runlab_slct.do           # Selection logic simulation
   do runlab_userin.do         # User input simulation
   

• SW[2:0]: Select column (3 bits for 7 columns)
• KEY[0]: Drop piece in selected column
• KEY[1]: Reset game
• LEDR[0]: Current player indicator (Red 0 / Green 1)
• LEDG[0]: Game status (Playing / Win)

• Modular Architecture: Each game component is a separate, testable module
• Hardware-Optimized Logic: Game logic implemented in combinational and sequential logic
• Real-time Rendering: VGA output updates in sync with game state
• Efficient State Management: 7×6 board stored in compact binary representation
• Timing Synchronization: Clock divider ensures proper synchronization across modules

• FPGA Device: Altera Cyclone V (5CSEMA5F31C6)
• Logic Elements Used: ~70% of available resources
• Timing: Meets all timing constraints at 50 MHz

• AI opponent implementation
• Sound effects via audio jack
• Difficulty levels
• Move history/undo functionality
• Network multiplayer via Ethernet

Developed for UW EE 271 - Digital Circuit and System Design, Winter 2025

Educational use. Redistribution and modification is permitted for educational purposes.

• Altera DE1-SoC User Manual
• Quartus II Design Software Documentation
• ModelSim User Guide
• SystemVerilog IEEE 1800-2017 Standard

Project Repository: https://github.com/nightplumeaki/DE1-SoC-connect-four