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.gitignore
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2030.mcs
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7seg_LEDs.vhd
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FMD2030_5-04A-B.vhd
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FMD2030_5-04D.vhd
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FMD2030_5-08B.vhd
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FMD2030_UDC1.vhd
FMD2030_UDC1.vhd
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FMD2030_UDC3.vhd
FMD2030_UDC3.vhd
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Gates2030.vhd
Gates2030.vhd
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IBM2030.xise
IBM2030.xise
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PH.vhd
PH.vhd
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PROM_reader_serial.vhd
PROM_reader_serial.vhd
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README
README
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README.md
README.md
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README.md~
README.md~
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RS232RefComp.vhd
RS232RefComp.vhd
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Testbench_panel_LEDs.vhd
Testbench_panel_LEDs.vhd
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Testbench_panel_Switches.vhd
Testbench_panel_Switches.vhd
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ccros.c
ccros.c
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ccros.vhd
ccros.vhd
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ccros20100715.txt
ccros20100715.txt
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ccros20120318.txt
ccros20120318.txt
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ccros20210925.txt
ccros20210925.txt
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clock_management.vhd
clock_management.vhd
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cpu.vhd
cpu.vhd
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digilentSP3.ucf
digilentSP3.ucf
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ibm1050.vhd
ibm1050.vhd
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ibm2030-cpu.vhd
ibm2030-cpu.vhd
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ibm2030-storage.vhd
ibm2030-storage.vhd
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ibm2030-switches.vhd
ibm2030-switches.vhd
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ibm2030-vga.vhd
ibm2030-vga.vhd
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ibm2030.bit
ibm2030.bit
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ibm2030.vhd
ibm2030.vhd
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panel_LEDs.vhd
panel_LEDs.vhd
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panel_Switches.vhd
panel_Switches.vhd
Dec 19, 2015
shift_compare_serial.vhd
shift_compare_serial.vhd
Apr 17, 2013
vga_controller_640_60.vhd
vga_controller_640_60.vhd
Apr 17, 2013

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IBM2030

An IBM System/360 Model 30 in VHDL

There are two main components to this release:

  • VHDL for the CPU (with 8k storage) and Multiplexer channel
  • The microcode image (4k x 55)

I am not claiming copyright to the microcode image - this is based on IBM manuals from 1964-1965 which may or may not be copyrighted themselves.

The VHDL is based on the IBM Maintenance Diagram Manual (MDM), which can be found on Bitsavers.

As supplied, the compiled system is suitable for a Digilent Spartan 3 board with a 1000K device, see http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD It uses the following I/O:

  • VGA output (8-colour, 3-bit)
  • Parallel I/O for switch scanning (10 out, 14 in)
  • On-board pushbutton inputs (4)
  • On-board slide switch inputs (8)
  • On-board LED outputs (8) If using an alternative board, it may be sufficient to modify the UCF file to reallocate inputs and outputs

These files can be compiled using the Xilinx ISE Webpack (and presumably other versions of the Xilinx suite). I have not tried compiling them with other VHDL compilers.

Apologies for the varied quality of the VHDL. This project has taken over 5 years and I have not necessarily re-visited code that was written early on. So there is a variety of styles and conventions. In my defence, it works (or seems to).

Lawrence Wilkinson lawrence@ljw.me.uk 2010/07/16

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An IBM System/360 Model 30 in VHDL

www.ljw.me.uk/ibm360/vhdl/

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