Arshiya Khatoon

Logic gates are the building blocks of digital circuits. They process binary inputs (0s and 1s) to produce specific outputs based on their function. The basic types include AND, OR, NOT, XOR, NAND, and NOR. These gates are used in everything from calculators to computers! #LogicGates #DigitalElectronics #EmbeddedSystems #Engineering #Tech

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1. What is CTS and why it's need? 2. Clock Routing Algorithms: -H-Tree -X-Tree •Method of Mean and Median •Geometric Matching Algorithms •Zero skew clock routing 3. Clock Latency/Insertion Delay: -source latency -network lacency 4. Skew: -Local skew -Global skew 5. types of skew: -positive skew -negative skew 6. Uncertainty 7. Jitter 8. Min Pulse Width: -min high pulse -min low pulse width -casues for pulse width and fixes 9. Differecne between clock buffer and normal buffer 10. Clock Gatting Technique 11. Synchronous and Asynchronous clocks 12. What is crosstalk and its types: -crosstalk noise -crosstalk delay: -positive corsstalk delay -negative crosstalk dealy -Redection technique 13. Checks Before Cts 14. Goals of CTS 15. Inputs of CTS 16. What SDC contains 17. Whta SPEC file contains: •Clock name Clock period Max skew and latency target values •Clock buffers and clock inverters information •NDR rules •Clock tree Exceptions. Information about Metal layers used 18. Clock Tree Exceptiopin Stop Pin • Non Stop Pin • Exclude Pin • Float Pin. Don't Touch pin 19. Non Defualt Rules: 2W.2S 20. CTS Flow 21. Useful commands in CTS 22. Clock Optimization Techniques 23. Checks after CTS 24. Outputs of CTS THANK YOU... 🙏🙏

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For students aspiring to intern at top-tier VLSI companies such as Intel, Qualcomm, Synopsys, Cadence, or NVIDIA, proficiency in Electronic Design Automation (EDA) tools is a game-changer. These platforms—spanning Synopsys Design Compiler, Cadence Virtuoso, Siemens Questa, and emerging open-source tools—are integral to every stage of the chip design cycle, from RTL coding and simulation to layout, verification, and timing analysis. Interns equipped with hands-on experience in these tools not only adapt faster to real-time workflows but also contribute effectively to live projects involving power optimization, signal integrity, and DRC/LVS compliance. Familiarity with these industry standards significantly boosts internship success, shortens onboarding time, and increases the likelihood of pre-placement offers from leading semiconductor firms.

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🔥🔥AXI Protocol 🌐The AXI protocol is one of the most commonly asked topics in job interviews, especially in ASIC and FPGA design verification roles. 💡 What's Inside? ✅ Key AXI protocol fundamentals ✅ Most frequently asked interview questions ✅ Simplified explanations for quick revision ✅ Essential insights for freshers and experienced professionals

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Department of ECE and EE (VLSI DT) at K.S.Rangasamy College of Technology jointly organizes a three-day hands-on workshop on "Chip Design: Accelerating AI Hardware with OpenPOWER" from October 07-09, 2025 @ VLSI Lab. Workshop Key Points: • Fundamentals of VLSI Design & AI Hardware Integration • Exploring OpenPOWER Architecture for Chip Design • Practical Hands-on Sessions with Industry Tools • Insights into Future Trends in AI Hardware #ksrct1994 #ksr #ksrei #ElectronicsEngineering #VLSIDesign #ChipDesign #OpenPOWER #AIHardware #Innovation #TechWorkshop #HandsOnLearning #FutureOfAI

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Learning is at the heart of every great internship experience. From exploring VLSI design and physical design to sharpening programming and problem-solving skills, interns in India embraced opportunities to grow their expertise while contributing to meaningful projects at Marvell. Through hands-on experience, collaboration and mentorship, they deepened technical knowledge and gained practical insights that will help shape their careers in technology. Their stories reflect the value of combining curiosity with real-world challenges and the impact of learning in action. Discover more about Marvell university programs: https://mrvl.co/3VEmGYp

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#LinuxForVLSI: Why It Matters for Chip Designers?? In the VLSI world, tools like Synopsys, Cadence, and Mentor Graphics run on Linux. Knowing how to work with Linux isn't optional-it's essential. Here’s how Linux is used in EDA tool workflows: ✅ Workspace Navigation – Engineers manage large HDL projects using command-line navigation for faster access. ✅ Editing & Debugging – Quick edits to Verilog/SystemVerilog files, constraints, and simulation scripts are done right in the terminal. ✅ Tool Setup – Before running tools, environment variables and paths are configured using shell commands. ✅ Simulation & Log Analysis – Engineers search simulation logs for errors/warnings using Linux tools instead of scrolling manually. ✅ Remote Access – EDA tools run on remote Linux servers; engineers connect securely and run jobs from anywhere. ✅ Automation – Shell scripting automates regression, synthesis runs, and other repetitive tasks. 🎯 Want to grow in RTL or DV? Get hands-on with Linux - it's your best ally in chip design! #VLSI #LinuxForVLSI #ChipDesign #RTL #SystemVerilog #EDA #Semiconductor #DV #LinuxSkills #Cadence #Synopsys #TheSiliconSandbox

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#100daysofRTL Hello , connections! Today I am starting my journey towards 100 days of RTL programming. DAY-1 Frequency Divider. Check my Git Hub repository:https://lnkd.in/gWFhBQjU Basic function : A "frequency divider" is a circuit that takes an input signal with a certain frequency and produces an output signal with a lower frequency, essentially "dividing" the original frequency by a specific factor; it's like creating a slower version of the original signal, often achieved by using logic gates like flip-flops in a specific arrangement to count the input pulses and generate a new pulse at a reduced rate.  Applications: Frequency dividers are used in various electronic applications like clock generation in microcontrollers, timer circuits, signal processing, and phase-locked loops (PLLs) where precise frequency control is needed. RTL and Test bench are coded and the waveform are generated using Xilinx Vivado software.

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💡 Did you know freshers in Embedded Systems & Semiconductors can earn up to 10x more than typical IT service roles? Most students only think of IT service companies (₹4–6 LPA) when they graduate… but the real game-changers are product-based companies in Embedded, VLSI, and Automotive Semiconductors. Here’s what the numbers actually look like 👇 ✅ Texas Instruments → ₹25–32 LPA ✅ Intel → ₹27–67 LPA (total comp packages) ✅ Qualcomm → ₹15–25 LPA ✅ Ciena → ₹16–25 LPA ✅ NXP, ON Semi, Bosch, Continental, Lear, Aptiv, Valeo → ₹10–20 LPA 🚀 Key Insight: The salary gap is HUGE — but so is the skill gap. While service companies focus on generic coding, these firms expect: Strong C programming fundamentals Basics of RTOS Hardware design + debugging knowledge Sharp problem-solving skills That’s why structured preparation makes all the difference. 📌 For anyone aiming 10+ LPA in Embedded/VLSI roles: Comment “Roadmap” below, and the free mentorship resources will be shared directly. Let’s raise the bar for freshers entering the core tech industry. 🚀 #EmbeddedSystems #Semiconductors #VLSI #Freshers #CareerGrowth #InterviewPreparation

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🚀 String Concepts in SystemVerilog Made Simple! While diving deep into SystemVerilog, I explored the powerful yet often overlooked string datatype—a dynamic type that handles ASCII-level data and resizes automatically! From classic methods like len, putc, getc, toupper, and tolower to the magic of $sformat, SystemVerilog strings offer strong utility—especially when dynamically naming variables during simulation! 💡 In this snippet, $sformat helps generate variable strings like env0 and env1 on-the-fly during iterations. Clean, efficient, and scalable! 🔧 Whether it's design automation or testbench scripting, understanding strings gives you a real edge in verification. 📍Shared as part of my daily learnings at PRSsemicon Technologies (A PRSGroup company) #LearnWithPrudhvi #SystemVerilog #VLSI #VerificationEngineer #DigitalDesign #HardwareDesign #CodingTips #TechTalk #ASIC #SoCDesign #EDA #Semiconductor #PRSsemicon

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Ready to ace your next Verilog interview? This comprehensive guide, "Verilog Interview Questions: From Basics to Advanced", is packed with 100 conceptual questions, clear answers, and example code to help you master Verilog for your next VLSI or ASIC design role. Topics covered include: ✅ Verilog Fundamentals: Differences between wire and reg, initial and always blocks, and blocking (=) vs. non-blocking (<=) assignments. ✅ Circuit Design: Modeling combinational and sequential circuits, latches, flip-flops, and counters. ✅ Advanced Concepts: generate blocks, parameters, tasks vs. functions, SystemVerilog assertions (SVA), and clock gating. ✅ Testbench & Simulation: Usage of $display, $monitor, timescale, and avoiding race conditions. Whether you're a beginner or looking to refresh your knowledge, this resource offers key takeaways and practical examples to strengthen your Verilog skills. Credit to the original creator! 🙌 #Verilog #VLSI #ASIC #DigitalDesign #InterviewQuestions #HardwareDescriptionLanguage #RTLDesign #FPGA #VerilogHacks

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Day 14:Routing Blockages in VLSI Design Good morning, Linkedin Family!!! Routing blockages are constraints that prevent or restrict the routing of nets through specific areas or layers of the chip. Types of Routing Blockages 1. *Hard Blockages*: Prevent any net from being routed through a defined region. 2. *Signal Blockages*: Prevent signal nets from routing through a region, but allow power nets (Vdd, Vss) to pass through. 3. *Layer-Specific Blockages*: Allow nets to be routed on certain layers but not others within a specific area. When to Use Routing Blockages 1. *Avoid congestion*: Prevent nets from being routed in densely packed areas. 2. *Enforce design rules*: Ensure that certain design rules are met, such as spacing or width requirements. 3. *Protect sensitive areas*: Prevent signal routing over sensitive areas, such as analog blocks. Benefits 1. *Improved routability*: Reduces congestion and improves routing efficiency. 2. *Increased design reliability*: Ensures reliable signal routing and reduces errors. 3. *Better design optimization*: Allows for more efficient use of routing resources. Let's Connect! Sharing insights on VLSI routing blockages and design optimization. #VLSI #RoutingBlockage #DesignOptimization #SemiconductorDesign

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