Kapil Dholakiya

Discover how InspireSemi successfully taped out their Thunderbird Accelerated Computing chip at 12nm using Cadence's Digital Full Flow, achieving best-in-class PPA and on-time design closure. The integration of Cadence's Tempus Timing Solution and Quantus Extraction Solution significantly reduced signoff closure iterations, allowing them to meet their tight tapeout deadlines faster. With such positive results, InspireSemi is excited to continue leveraging the digital full flow for future projects. Together, we're paving the way for the next generation of high-performance computing and AI! Watch the full episode here: https://ow.ly/Unf650UcbFc

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Our Thunderbird system-on-chip (SoC) is disrupting the next generation of accelerated compute on many levels, including raw performance, broad applicability, lower energy consumption, ease of programming, and affordability. Cadence's Digital Full Flow played a crucial role in the successful tapeout of the Thunderbird SoC. #hpc #ai #linux #openmp #mpi

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Paging in memory subsystem: Paging is a memory management scheme that eliminates the need for contiguous allocation of physical memory, thereby minimizing fragmentation and allowing more efficient use of available memory resources. 👉 Basic Concepts in Paging 1️⃣ Pages and Frames Pages: The virtual memory is divided into fixed-size blocks called pages. These are typically 4KB in size, though sizes can vary. Frames: The physical memory is similarly divided into fixed-size blocks called frames, which are the same size as pages. 2️⃣ Page Table: A data structure used to keep track of the mapping between virtual pages and physical frames. Each process has its own page table, which translates virtual addresses to physical addresses. 3️⃣ Page Table Entry: Each entry in the page table contains information about a specific virtual page, including the frame number it maps to, access permissions, and status bits (e.g., present, modified). ✅ Components Involved in Paging 1️⃣ Memory Management Unit (MMU): The MMU is a hardware component that handles the translation of virtual addresses to physical addresses, utilizing the page table and TLB (Translation Lookaside Buffer). 2️⃣ Translation Lookaside Buffer (TLB): A cache used by the MMU to speed up address translation by storing recent translations of virtual addresses to physical addresses. If a virtual address is found in the TLB (TLB hit), translation is fast. If not (TLB miss), the page table must be consulted. 3️⃣ Page Tables: Each process has its own page table, managed by the operating system. The page table contains entries for each page in the virtual address space, mapping them to physical frames. 👉 Paging Mechanisms 1️⃣ Single-Level Paging: The simplest form of paging where a single page table is used for address translation. Suitable for small address spaces but inefficient for large address spaces due to large page tables. 2️⃣ Multi-Level Paging: Hierarchical paging where the page table is divided into multiple levels. This reduces the memory overhead for page tables in large address spaces. 3️⃣ Inverted Page Table: A global page table that contains one entry for each frame of physical memory, mapping physical addresses to virtual addresses. It reduces the size of the page table but can be slower due to the need for searching. 🌟 Benefits of Paging 1️⃣ Efficient Memory Use: Paging allows non-contiguous allocation of physical memory, reducing fragmentation and making better use of available memory. 2️⃣ Isolation and Protection: Each process operates in its own virtual address space, isolated from others, enhancing security and stability. 3️⃣ Scalability: Paging supports large virtual address spaces, allowing modern operating systems to manage memory for multiple processes efficiently. 4️⃣ Ease of Allocation: Fixed-size pages and frames simplify memory allocation and deallocation, as any free frame can satisfy a page request. Credit : Gopal Chakraborty #memory #embedded #vlsiforall

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The electrical specifications for PCIe (Peripheral Component Interconnect Express) are critical to ensuring high-speed data transfer, signal integrity, and compatibility across devices. Below is an overview of the key electrical parameters for PCIe across various generations. PCIe Electrical Specifications 1. Voltage Levels PCIe Standard Voltage: 3.3 V for signaling (control logic), with 12 V for auxiliary power in some configurations. I/O Signaling: Differential Pair Signaling: PCIe uses Low Voltage Differential Signaling (LVDS) with typical voltages around 0.8 Vpp (peak-to-peak) for each lane. 2. Differential Pair Characteristics Differential Signaling: PCIe lanes consist of pairs of signals (e.g., TX+/TX-, RX+/RX-). Data is transmitted as the voltage difference between the positive (P) and negative (N) lines, reducing noise and crosstalk. Impedance: 85 Ω ± 15% (differential impedance) on the transmission line. #Capacitor #Electronics #PassiveComponents #Capacitance #ElectricalEngineering #Resistor #PassiveComponents #Resistance #Inductor #Inductance #ElectronicsDesign #CircuitDesign #PCBDesign #HardwareDesign #PCB #PCBLayout #CircuitLayout #ElectronicsLayout #ElectricalEngineering #EmbeddedSystems #TechDesign #Engineering #Engineering #Electronics #HardwareDesign #PCBDesign #EmbeddedSystems #IoT #CircuitDesign #PowerElectronics #DCDCConverter #SignalIntegrity #HighSpeedDesign #AnalogDesign #DigitalDesign #OrCAD #Cadence #AltiumDesigner #KiCAD #Ethernet #PCIE #DDR #I2C #UART #SPI #Tech #Innovation #STEM #CareerGrowth #ProfessionalDevelopment

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Detailed review of Xeon 6 (Granite Rapids). Summary from the conclusion: "Intel has finally solved its core count issue, while also offering things like AMX, QAT, and more for acceleration, high-end DDR5 and MRDIMM (MCR DIMM) solutions for big memory bandwidth, and more. Intel lost its top-end edge when it lost process leadership with 10nm and Ice Lake. As the manufacturing and packaging side has improved, Intel is back in the fight. Welcome back Intel." #intelxeon https://lnkd.in/g-CfuTRj

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The MediaTek Dimensity 6300 brings a  performance boost, great gaming, and vibrant visuals to mainstream 5G smartphones. The Dimensity 6300 packs a powerful punch into a very tiny chip. Features include:  📸 108MP cameras with enhanced noise reduction   🎮 Faster games (up to 10% faster FPS than the previous generation and 50%+ GPU performance over the competitors)   🌈 Billion color displays with vibrant AMOLED and displays speeds of up to 120Hz 📡 Premium 5G technologies, including fully integrated 5G modem with downlink speeds up to 3.3Gb/s   🔋 Exceptional power efficiency thanks to TSMC 6nm-class chip production #MediaTek #MediaTekDimensity6300 #mainstreamsmartphones #Dimensity #5G

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Advanced and rich IP portfolio The continuous evolution of process technology and the increased integration capabilities of EDA tools allow designers to integrate more complex functions into the chip. Intellectual property (IP) continues to make influence the quality of design, time to market, and cost, making it an integral part of a product's competitive advantage. VeriSilicon maintains high R&D investment to create a rich IP portfolio: In-house Graphics Processor Unit (GPU) IP, Neural Network Processor (NPU) IP, Display Processor IP, Video Processor Unit (VPU) IP, Digital Signal Processor (DSP) IP, and Image Signal Processor (ISP) IP A comprehensive analog semiconductor IP portfolio covers process nodes from 180nm to 7nm, as well as advanced ultra-low power analog IP solutions A variety of digital-analog interface IP from 250nm to 5nm process nodes, including MIPI, USB, PCIE, etc. A variety of ultra-low power RF IP, including low power Bluetooth (BLE) IP and narrowband Internet of Things (NB-IoT) IP Customized standard cell library for foundry processes Coupled with our third-party IP partner eco-system, VeriSilicon brings advanced IP solutions to our customers. Our IP portfolio is silicon proven, production proven and application proven. This demonstrates VeriSilicon's commitment to continually improve IP quality and strive for our customers' success. Vivante® GPU IP VeriSilicon's scalable Vivante Graphics Processor Unit (GPU) IP Series can be used in a wide range of applications, from LPC (low-power-consumption) small IoT MCUs to powerful SoCs for automotive and computer applications. Read More Vivante® Display Processor IP VeriSilicon’s product-proven Vivante Display Processor IP Series offer display processing functionality including rotation, data formation conversion, HDR video processing and high-quality video scaling, as well as processes HDR layer and graphic layer composition to release high visual quality and reduce silicon power significantly. Read More Vivante® NPU IP VeriSilicon's Neural Network Processor (NPU) IP is a highly scalable, programmable computer vision and artificial intelligence processor that supports AI operations upgrades for endpoints, edge devices, and cloud dev ZSP® DSP IP VeriSilicon's programmable ZSP Digital Signal Processor IP is a series of processor cores optimized for signal processing computation and data streaming, for building cost effective embedded solutions for a wide range of applications, including audio, voice, imaging, vision, wireless connectivit RF IP VeriSilicon has developed a variety of ultra-low-power-consumption RF IP for IoT applications, including BLE 5.0, NB-IoT, 802.11x, and 22nm FD-SOI and other china #europe #buy #globalbusiness #headhunter #usa #automotive #automotiveindustry #leadership #motivation ]#personaldevelopment#employment #happiness #jobs #health #global #world #jobchange #process #plasma #Knlowledgestudy #buyer #globalbusiness #Tec

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More Awe-inspiring Learning from ESD Failure: ESD failure in silicon product is a great leveler. It forces you to rapidly traverse the grief cycle and get to acceptance and a solution. But don't forget the awe-inspiring learning on the journey 😀. Here is another one that provided this opportunity. We were devising a high voltage self-protecting LDMOS-based ESD clamp but it showed a curious (and very dangerous) "walk-in" of the snapback trigger voltage. Failure analysis showed amazing filamentation. Check out the metal within one of the filaments. The clamp would actually pass a Human Body Model but Transmission Line Pulsing showed a gradual collapse of the Safe Operating Area. After we fixed it we delved more deeply into the failure mechanism. It was all consistent with a growing filament that eventually reached through the lightly doped junction. All a bit analogous to electrical breakdown of solids/dielectrics and "treeing". Thank goodness for the learning! #ESD #ElectrostaticDischarge #FA #FailureAnalysis

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Dear Keysight Technologies, please don't 🙅‍♀️lay off anybody at Synopsys Optical Solutions Group (formerly RSoft Design Group) / Synopsys​ Optical Solutions. Not 1 person. They're magical 🧙‍♂️ superstars and we need all of them. A few days ago, news broke about  Synopsys' optics 🔦📸 stuff getting sold to Keysight, likely to let  the Synopsys takeover of Ansys  happen  without it getting stopped 🛑 by those annoying (j/k)  antitrust laws. I learned the news 📰 from Julius Muschaweck's post and was 1 of the nerds 🤓 that wrote the FTC about why if ALL THE OPTICALS BELONG TO SYNOPSYS  would be scary 😱 -- thanks to Max Henkart's public pleas to other optical engineers  to join his letter-writing 📩 efforts. This may be great news! BUT one thing I worry 😬 about -- is the prospect of losing any of the  critically valuable  knowledge 🧠 and people  to layoffs/restructuring. So Keysight,  in case you aren't aware  (but I really hope you are) optical simulations and the software associated is more like an artform 🎨 than a TI-89 calculator. 📲 It takes years 🗓️🗓️🗓️ of working with it to know how to best make it fit real-world 🌎 results. It takes even more years of experience to guide 👨‍🏫 others and explain the deeper levels of its functioning.  It isn't all completely explained in a manual 📖 somewhere. All the pros 😎🤩😏🥸😇 at Synopsys Optical Solutions Group are important, integral parts of the tools 🪛🛠️ you'll be selling. Please keep every precious one! #opticalengineering #simulations #optics #illumination #imaging #lighttools #codev #lucidshape #zemax #speos #lighting #ansys #synopsys #keysight

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Explore the future of technology with the latest trends in VLSI! AI is transforming design, testing, and verification, while energy-efficient circuits are powering mobile and IoT devices. Modular chiplets bring flexibility and faster production, and vertical IC stacking boosts performance by reducing delays. With hardware security integration, chips are now more protected than ever. Plus, advancements in VLSI are driving innovation in flexible and wearable tech! Stay ahead of the curve with these groundbreaking developments. Ready to transform your future in VLSI? Enroll now at Teks Academy – The Best Software Training Institute in Hyderabad and take the first step toward success! #vlsi #vlsicourse #verylargescaleintegration #trendingcourses #vlsidesign #verification #testing #chiplets #hardware #microchips #chip #circuit #integratedcircuits #transistors #diodes #semiconductor #circuits #electricalengineering #electronics #chipdesign #vlsitraining #courses #training #institute #coaching #design #techniques #clocksignal #teksacademy #academy #hyderabad #vlsidesign #voltage #frequency

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Good Opportunity

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Teledyne LeCroy PCIe 6.0 M616 Exerciser / Analyzer Demo - Flit mode traffic generation at 64.0 GT/s with PAM-4 signaling. https://lnkd.in/g_GBp-yp

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Sharing insights on gamma ray detection circuits and the technology behind them! #Electronics #Engineering #LowNoiseJFETs #GammaRayDetection"

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Explore the key types of amplifiers used in sensor signal chains and their applications, from transimpedance amplifiers to charge and voltage amplifiers. Learn how they enhance performance and reliability in various sensor systems. [Read the full post on Linear Systems' page.](#) https://lnkd.in/diQtZ9VW

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