Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores

Publisher: IEEE

Abstract:In the Internet-Of-Things (IoT) domain, microcontrollers (MCUs) are used to collect and process data coming from sensors and transmit them to the cloud. Applications that...View more
Abstract:
In the Internet-Of-Things (IoT) domain, microcontrollers (MCUs) are used to collect and process data coming from sensors and transmit them to the cloud. Applications that require the range and precision of floating-point (FP) arithmetic can be implemented using efficient hardware floating-point units (FPUs) or by using software emulation. FPUs optimize performance and code size, whilst software emulation minimizes the hardware cost. We present a new area-optimized, IEEE 754-compliant RISC-V FPU (Tiny-FPU), and we explore the area, code size, performance, power, and energy efficiency of three different implementations of the RISC-V Instruction Set Architecture double and singleprecision FP extensions on an MCU-class processor. We show that Tiny-FPU, in its double and single-precision versions, is respectively 54% and 37% smaller than a double and singleprecision FPU optimized for performance and energy efficiency. When coupling a RISC-V core with Tiny-FPU, we achieve up to 18.5x and 15.5x speedups with respect to the same core emulating FP operations via software.
Date of Conference: 22-28 May 2021
Date Added to IEEE Xplore: 27 April 2021
Print ISBN:978-1-7281-9201-7
Print ISSN: 2158-1525
INSPEC Accession Number: 20730137
Publisher: IEEE
Conference Location: Daegu, Korea

I. Introduction and Related Work

The era of the Internet of Things (IoT) is characterized by billions of devices gathering data from sensors and sending them to powerful servers, where analysis and pattern extraction is performed using intelligent algorithms. To save bandwidth and energy across the whole network infrastructure, IoT devices can pre-process sensor data with advanced algorithms like filters and compressors [1], giving birth to so-called edge computing devices. Such algorithms differ in complexity, ranging from requiring only a few integer or fixed-point operations to performing dense kernels using floating-point (FP) arithmetic.

References

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