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I noticed often times the external crystals frequency is multiplied to arrive at a microcontroller's clock speed. Why is this done?
Take, for example, the TI CC2650. In its default configuration, it uses a 24 MHz crystal to arrive at a 48 MHz clock frequency. 48 MHz crystals are widely available, so why not use that?
Would this not also double the tolerance range of the crystal?
As crystal frequency gets higher, dimensions get smaller (especially thickness). Above roughly 50 MHz, AT-cut crystals become fragile, and manufacturers use third-overtone cuts for higher frequencies...some even use 5th-harmonic.
These "overtone" crystals are susceptible to rogue resonances...for really careful designers additional inductor, capacitor elements might be added to encourage oscillations at the desired frequency. Oscillator design is tricky enough, even without these extra efforts.
Crystal oscillators have a robust engineering history below 10 MHz. Microcontroller designers take advantage of robust external oscillators below 10 MHz, and then internally boost frequency with phase-locked loops. It seems that the internally-integrated PLL's are well-under-control of chip designers - go figure.
Even so, sub-10 MHz crystal are now being cut smaller, which raises circuit impedances, making oscillator designs more susceptible to adjacent electric fields and transient events. If you need tight control of tolerances, use a canned oscillator unless you want to expend significant engineering effort designing your own.
Are you really confident-enough to characterize the operating envelope of your own oscillator design?
48 MHz crystals are widely available, so why not use that?
That 48 MHz crystal is possibly a 3rd overtone type. There is some risk of it oscillating near 16 MHz (fundamental frequency) instead. There are also spurious resonant frequencies that increase somewhat the risk of off-frequency oscillation. I would suggest that safe-operating envelope of a 48 MHz overtone oscillator is smaller than the safe-operating envelope of a sub-10 MHz fundamental oscillator - followed by the PLL frequency-multiplier inside the microcontroller.
Here is an example of how a crystal manufacturer cuts crystals. At the low-frequency end of the range, fundamental resonance is more active than 3X, 5X, 7X...harmonic resonances. Only above 42 MHz does the manufacturer ensure that the 3X resonance dominates:
would this not also double the tolerance range of the crystal?
Data-sheet tolerance applies to the 48 MHz operating resonance: read the data sheet!
That is because it is easier to use a low frequency crystal as a reference for any arbitrary frequency you want to run the MCU at, like higher frequencies such as few hundred MHz or even slower than the crystal.
And crystals such as 48 MHz exist but are usually quite different from crystals below 30 MHz. It will be more difficult to make a fast crystal work than a slow crystal. And approximately above 30 MHz the crystals are used in overtone modes which makes the oscillating circuit more complex.
And it won't multiply the tolerance. If you have a frequency X with 100 ppm tolerance, and multiply by any amount, it will still have 100 ppm tolerance.
A crystal is rarely used at its native frequency. Its main purpose is to provide a system timebase, so that everything derived from this crystal will agree on the exact time. For this purpose, the native crystal frequency is irrelevant. What is important is how well it maintains its frequency (stability and to lesser extent jitter). And even that is mostly important for the communication with other timebases.
As you usually need several different frequencies (at least inside logic ICs), you anyway need the PLL step, so it becomes even more irrelevant at which frequency you start.
So you just choose the easiest, most convenient crystal frequency and derive everything from it using essentially free PLLs. Lower frequencies use less power, higher frequencies have less jitter. The compromise is often in the 10-20 MHz ballpark.
Besides the practicalities of crystals themselves, there is also the matter of the logic interface. To be clear, silicon oscillators are also available with crystal-level stability, and in high frequencies. Why not use them?
Well, cost for one; they might not be as cheap as quartz or other resonator based oscillators. But besides that, too:
Most MCUs work with CMOS logic levels, at relatively high supply voltages (3.3+ V). Every switching edge must push the capacitance of its pin driver, the connecting trace, and the receiving pin, more or less fully from rail to rail. At low frequencies, this is fine, but as frequency goes up, rise time must get faster and faster to maintain low jitter, and the power consumption of all that voltage swing keeps going up.
For example, a 10 pF pin plus trace capacitance (which is probably fairly typical, or maybe on the low side, for a typical short distance between oscillator and MCU, and their typical pins), dissipates or 55 pJ per switching edge. At 10 MHz, this is 550 µW, not a big deal in the grand scheme of things, but definitely an annoyance for a battery-operated device, say. And at 100 MHz, it's 5.5 mW. Still hardly going to start a heat wave, but it also adds up quickly when compared with the power-efficient on-chip logic (that might be running at 1.2 V even, and is made from truly microscopic transistors with nearly negligible capacitances). Meanwhile, you've got traces on the board that are making electrically-short antennas, and driving a couple volts into them at 100 MHz or whatever means you're going to get, not a great amount of radiation, maybe it's -40 dB gain or whatever — but when your limit is -60 dBµV say, now you're over the limit by the ballpark of say +20 dB!
At still higher frequencies, power consumption and EMI become burdensome, and LVDS or ECL signaling becomes more efficient. These use a small current or voltage swing, thus incurring less power dissipation pushing around capacitances, and are matched-impedance (which, actually, we're not pushing around capacitance at all anymore, or not primarily anyway, but rather the characteristic impedance of a transmission line — meanwhile, edge rates are fast enough that transmission line behavior is relevant to signal quality analysis, even for fairly short runs). Meanwhile, particularly for differential (LVDS, etc.), the complementary traces mean radiation is largely canceled out, except very near the traces, or if the run ends up unbalanced (length matching is important, as is avoiding nearby traces / floating copper / etc. which can couple to one trace more than the other and increase radiation).
Alternately, we could remove the square wave harmonics so we don't have to switch fully back and forth all the time — indeed, we can go further and use a resonant circuit to null out the pin/trace reactance and pass around a high-frequency sine wave with almost arbitrarily low power consumption. But this makes the transmitter and receiver much more complicated: the transmitter must be internally filtered and able to supply continuous analog levels; and the receiver needs a comparator to recover sharp digital edges, or an RF mixer based PLL to use the sine wave directly. And needless to say, we lose the nice property of digital logic (trace length ~doesn't matter, at worst we only need to worry about source and/or load termination resistances) and suddenly need a ton of finicky tuning reactances on the board.
That said, sine-wave oscillators are available, too. There are indeed sine-input PLLs, or if you're working with a radio system, the sine might be used directly by a mixer.
