In the beginning of 1980's, DEC was on the paramount of its financial strength mostly because of high revenues related to growing constantly sales of VAX hardware and software. Of course, nothing lasts forever, and it was obvious that some day VAX would have to leave the market in favour of a more sophisticated and flexible architecture as it was happening with PDP-11. Those days many companies started to pay more and more attention to RISC-based concepts and implementations, so DEC had no intention to ignore that trend. There were several development teams inside of DEC between 1982 and 1985 which researched actively over the RISC arena:

• Titan, a high-speed design developed at Western Research Laboratory (DECwest) in Palo Alto (California, the USA) and supervised by Forest Baskett, since 1982;
   
• SAFE (Streamline Architecture for Fast Execution), a project supervised by Alan Kotok and David Orbits, since 1983;
   
• HR-32 (Hudson RISC 32-bit), developed at the semiconductor factory of DEC in Hudson (Massachusetts, the USA) and supervised by Richard Witek and Daniel Dobberpuhl, since 1984;
   
• CASCADE, a project by David Cutler in Seattle (Washington, the USA), since 1984.

In 1985, after Cutler's initiative on creating a so-called corporate RISC plan, all 4 projects were merged into a single one called PRISM (PaRallel Instruction Set Machine), and the first draft for a new RISC processor was released in August of 1985. To mention, DEC participated in development of the MIPS R3000 processor those days and even initiated creation of Advanced Computing Environment consortium to promote the MIPS architecture.
 
No wonder that the new processor inherited many features of the MIPS architecture, though the differences were also obvious. All instructions were fixed-length at 32 bits with the upper 6 and the lower 5 ones presenting an instruction code and the remaining 21 were reserved for immediate data or addressing needs. There were 64 primary 32-bit general-purpose registers defined (MIPS required 32), 16 additional 64-bit vector registers and 3 control registers for vector operations: two 7-bit (vector length and vector count) and one 64-bit (vector mask). There was no processor state register, thus a result of two scalar operands compared was written into a general-purpose register, but a result of two vector operands compared — into the vector mask. There was no built-in floating-point unit. A set of special instructions called Epicode (Extended processor instruction code) was maintained in software through loadable microcode to facilitate handling of special tasks required for a particular environment or operating system given and not supported by the standard instruction set otherwise. Later, this function was implemented in the Alpha architecture under the name of PALcode (Privileged Architecture Library code).
 
In 1988, when the project was still in progress, top managers of DEC decided to close it considering any further support as a waste of resources. Protesting against that decision, Cutler resigned and went to Microsoft to supervise a department developing Windows NT (called OS/2 3.0 those days).
 
In the beginning of 1989, DEC presented first RISC-powered workstations of its own, DECstation 3100 with a 32-bit MIPS R2000 inside clocked at 16MHz, and DECstation 2100 with the same processor but clocked at 12MHz. Both machines were running Ultrix OS and were priced rather inexpensively. For instance, it took about 8000 USD (1990) for a DECstation 2100 configured regularly.

In 1989, the aging VAX architecture was hardly able to compete with RISC architectures of the 2nd generation such as MIPS and SPARC. It was obvious that the next generation of RISC hardware would leave not so many chances for VAX to survive. In the middle of 1989, DEC's engineers received a task to create a competitive RISC architecture with a long-term potential, but carrying a minimal set of incompatibilities with VAX at the same time. That was because VAX/VMS and all accompanying applications had to be ported to the new architecture which was also defined to be 64-bit right from the start since competitors were about to release their 64-bit solutions. A development group was created with Richard Witek and Richard Sites involved as the chief architects.
 
The Alpha architecture was mentioned officially for the first time on the 25th of February 1992 during a conference in Tokyo. In addition, most important features of the new architecture were listed within a concise overview for comp.arch, a USENET conference. It was also mentioned that "Alpha" was an internal code-name and an official name had to be provided later. The new processor was of a "clean" 64-bit RISC design to execute fixed-length instructions of 32 bits each. It accommodated 32 64-bit integer registers, operated with 43-bit virtual address space which could be expanded for up to 64 bits in future hardware implementations. Like VAX, it preferred little-endian byte order (i. e. when the least significant byte of a register occupies the lowest memory address if stored; was promoted by Intel in contrary to big-endian byte order, introduced by Motorola and employed by most processor architectures of those days, when the most significant byte of a register occupies the lowest memory address if stored). A mathematical co-processor was built into the core together with 32 64-bit floating-point registers which utilised random access order unlike primitive stack access order implemented in Intel x87 co-processors. The total lifetime of the new architecture was estimated in no less than 25 years.
 
The instruction set was simplified to facilitate pipelining actions as much as possible and consisted of 5 groups:

• integer instructions;
• floating-point instructions;
• branch and compare instructions;
• load and store instructions;
• PALcode instructions.

To mention, there was no hardware support for integer divide instructions because they would be the most computationally-expensive integer ones and thus badly pipelineable, so they were just emulated. It was an acceptable solution because integer divide was used relatively not so often in real life, especially considering that shift instructions were able to satisfy many integer divide and multiply calculations.
 
Alpha architecture was a real RISC in contrary to different x86 microarchitectures of the past and present starting with NexGen 586, Intel P6 and AMD K6. In fact, they were RISC on the level of processor functional units only. The conceptual difference between RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) was (and still is) within a few moments:
 

Feature	CISC	RISC
Instruction length	Variable, depends upon instruction type	Fixed, doesn't depend upon instruction type
Instruction set	Large, adapted for programmer's needs	Medium, adapted for processor's execution convenience
Memory access	Allowed for different kinds of instructions	Allowed for load/store instructions only

Note: This table applies to general purpose processors only because DSPs and other embedded ASICs are much different. For instance, their instruction sets are small typically because of high level of specialisation.
 
The processor was supposed to be launched in production at a very high core frequency — 150MHz — which was planned to be increased for up to 200MHz while utilising the same engineering limits. It appeared to be possible because of a successful architecture as well as because engineers who developed the processor rejected to involve automatic design systems and did all work just manually. The project entered manufacturing stage and was reorganised into a regular division of DEC soon after.
 
Because of DEC marketing department's efforts the new architecture was called AXP (or Alpha AXP), though still not known for sure what exactly this misunderstanding meant. Quite possible that nothing at all. In the past, DEC had legal problems with its VAX brand because there was another pretending company, a manufacturer of vacuum cleaners, and the conflict was taken to court that time. By the way, it was also motivated that sales of DEC equipment suffered because of the other company's reasonable slogan, "Nothing sucks like a Vax!" After all, a joke showed up saying that AXP meant "Almost eXactly PRISM".