I. Introduction

All-optical sequential elements are the key components of the next generation photonic memory elements [1], registers [2], packet switching element [3], PRBS generator [4] etc. Flip-flops are the basic sequential elements. Delay flip-flop is a simplest form of sequential circuit which overcomes the ambiguity of the forbidden state of set-reset flip-flop that occurs when both set and reset inputs are set high (‘‘logic-1’’) state. In finite state machines D flip-flop is usually chosen to perform the memory circuit because its input presents the same value as the variables at the next stage according to clock input. The clock controls all flip-flops to sample and store their input data synchronously. Low (‘‘logic-0’’) and high (‘‘logic-1’’) levels of the clock signal put a latch in either a storage state or an input state. Two types of D flip-flop can be designed, one is positive edge triggered (PET) and other is negative edge triggered (NET). Both FFs are important in communication system, particularly in energy saving dual edge triggered flip flop, where data can be stored in both positive and negative edge of the clock [5].