(cache)RISC-V Foundation | Instruction Set Architecture (ISA)

Calling all embedded designers! Participate in the RISC-V SoftCPU Contest to create innovative FPGA soft CPU implementations with the RISC-V ISA. You could win up to $6,000 USD! Submissions are due Nov. 26. Learn about the contest details and rules here.
The inaugural RISC-V Summit will be held in Santa Clara, Calif. from Dec. 3-6, 2018, featuring keynote speakers from Antmicro, Facebook, Microchip Technology, NXP, SiFive and Western Digital. Promotional pricing ends on Oct. 29. Register here and learn more about the RISC-V Summit here.
Want to know what happened at the latest RISC-V events? Check out the proceedings: RISC-V Workshop in Barcelona (May 2018), RISC-V Day in Shanghai (June 2018) and RISC-V Workshop in Chennai (July 2018). You can also check out the proceedings from the RISC-V Foundation booth at DAC (June 2018).
Join the Bay Area RISC-V Group on Meetup to check out activities happening in the San Francisco Bay Area, and the Rocky Mountain RISC-V Group for activities around Colorado. Coming up next is the Cambridge RISC-V Meetup on Tuesday, Nov. 20 at 6 p.m. at Westminster College Cambridge in Cambridge, UK.
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RISC-V: The Free and Open RISC Instruction Set Architecture

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

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RISC-V Ecosystem Events

RISC-V Foundation Announces Initial Keynote Speakers For Inaugural RISC-V Summit

September 10, 2018

The RISC-V Foundation, a nonprofit corporation controlled by its members to drive the adoption and implementation of...

RISC-V Foundation Announces Call For Papers And Registration Promotions For Inaugural RISC-V Summit

August 6, 2018

RISC-V Workshop in Chennai Proceedings

July 19, 2018

RISC-V Foundation Announces Agenda For RISC-V Workshop In Chennai

July 10, 2018

RISC-V Foundation at Design Automation Conference (DAC) Proceedings

July 5, 2018

RISC-V Ecosystem News

Moortec’s 7nm In-Chip Monitoring Subsystem IP Chosen By Esperanto Technologies To Optimize Performance And Reliability In Its High-Performance AI Chip

November 13, 2018

Moortec Semiconductor Ltd, providers of complete In-Chip PVT Monitoring Subsystems announced today that Esperanto Technologies have selected their complete 7nm Embedded In-Chip...

LinuxGizmos.com Article: Linux-Driven 96Boards SBC Features AI And RISC-V Companion Chips

November 13, 2018

Bitmain announced a “Sophon BM1880 EDB” 96Boards CE SBC featuring its new Sophon BM1880 AI chip plus dual Cortex-A53 cores that run Linux. There’s also a RISC-V MCU and...

lowRISC Blog Post: Tutorial For The v0.5 lowRISC Preview Release

November 13, 2018

lowRISC is a non-profit organization whose goal is to produce a fully open source System-on-Chip (SoC) in volume. We are building upon RISC-V processor core implementations from...

ABI Research Insight: Watch Out For “Made In China” Open Source Artificial Intelligence Chipsets

November 13, 2018

In September 2018, Xiaomi-backed Huami launched the world’s first AI wearable chipset based on RISC-V architecture. The launch of the chipset brings a lot of promise for...

Andes Technology And INVECAS Announce Partnership To Win RISC-V-Based SoC Designs For Advanced Processes

November 13, 2018

Andes Technology Corporation, a leading supplier of small, low-power, high performance 32-/64-bit embedded CPU cores, and INVECAS, a provider of leading edge IP solutions, design...

RISC-V Foundation Members

Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Through various events and the Foundation's Workshops, the RISC-V Foundation is changing the way the industry works together and collaborates – creating a new kind of open hardware and software ecosystem. Become a member today and help pioneer the industry’s future de facto ISA for design innovation

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RISC-V: The Free and Open RISC Instruction Set Architecture

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