9560NG Intel Dual Band Wireless-AC 9560 User Manual Intel® Wireless-AC 9560 (Jefferson Peak) ASUSTeK Computer Inc
ASUSTeK Computer Inc Intel Dual Band Wireless-AC 9560
Intel® Wireless-AC 9560 / 9560NGW (Jefferson Peak) External Product Specification (EPS) April 2017 Revision 1.0 Intel Confidential Document Number: 567240–1.0 Notice: This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential April 2017 Document Number: 567240–1.0 Contents Introduction ................................................................................................................. 8 1.1 Key features ........................................................................................................ 8 1.2 Jefferson Peak module SKUs ................................................................................. 10 Product Architecture................................................................................................... 11 2.1 Integrated Connectivity concept ............................................................................ 11 2.1.1 MAC-PHY split .................................................................................... 11 2.1.2 SoC and Companion RF compatibility..................................................... 11 2.1.3 Swappable Companion RF/Discrete ....................................................... 12 2.2 Jefferson Peak interfaces ...................................................................................... 12 Electrical Specifications .............................................................................................. 14 3.1 2230 and 1216 form factor pinouts ........................................................................ 14 3.2 Input/output electrical specifications ...................................................................... 22 3.3 Peak current consumption .................................................................................... 24 3.4 M.2 power and ripple limits ................................................................................... 24 3.4.1 Power supply ripples ........................................................................... 24 3.4.2 Platform state transitions ..................................................................... 25 3.5 M.2 ground (GND) ............................................................................................... 25 Mechanical Specifications ........................................................................................... 26 4.1 Weight ............................................................................................................... 26 4.2 M.2 2230 mechanical specification ......................................................................... 26 4.3 M.2 1216 mechanical specification ......................................................................... 27 4.4 Z height ............................................................................................................. 29 4.5 M.2 antenna retention .......................................................................................... 29 4.5.1 Recommended method for retention of M.2 cable.................................... 29 Performance ............................................................................................................... 30 5.1 Power consumption.............................................................................................. 30 5.1.1 Wi-Fi power consumption ..................................................................... 30 5.1.2 BT power consumption ........................................................................ 31 5.2 Wi-Fi performance ............................................................................................... 32 5.2.1 Wi-Fi Tx power (TBD) .......................................................................... 32 5.2.2 Wi-Fi sensitivity .................................................................................. 36 5.2.3 Wi-Fi throughput targets ...................................................................... 37 5.3 Bluetooth performance ......................................................................................... 38 5.3.1 Bluetooth Tx power (TBD) .................................................................... 38 5.3.2 Bluetooth sensitivity (TBD) .................................................................. 38 5.3.3 Bluetooth throughput targets ............................................................... 39 Thermal Specifications ............................................................................................... 40 6.1 Thermal dissipation.............................................................................................. 40 6.2 Thermal specifications .......................................................................................... 40 6.3 Thermal management .......................................................................................... 40 6.4 Module placement recommendations...................................................................... 41 6.5 Nonoperational module thermal storage ................................................................. 41 Regulatory .................................................................................................................. 42 7.1 Regulatory channel support and output power......................................................... 42 7.2 Wi-Fi channel configuration ................................................................................... 42 7.2.1 Channel configuration – RF output power ............................................... 42 7.2.2 Channel configuration – scan ................................................................ 42 7.2.3 Output power restrictions for main geographies ...................................... 42 7.3 Regulatory and safety certification ......................................................................... 43 April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 8 Dynamic Regulatory Solution ...................................................................................... 45 8.1 Overview ............................................................................................................ 45 Platform Design Guidelines......................................................................................... 46 9.1 Socket 1 key options for 2230 cards ...................................................................... 46 9.1.1 Socket 1 Hybrid Key E scheme ............................................................. 46 9.1.2 Connectorized Hybrid Key E (2230) pin-out ............................................ 47 9.1.3 Special considerations for the Hybrid Key E scheme ................................ 48 9.1.4 Soldered-down (1216) pin-out.............................................................. 51 9.1.5 Breakout example for JfP soldered-down module .................................... 53 9.1.6 Signal connection pitfalls ..................................................................... 55 9.1.7 Pullups and pulldowns ......................................................................... 55 9.1.8 IO connection scenarios and best practices ............................................ 56 9.1.9 I/F specific guidelines .......................................................................... 56 9.1.10 Connectivity module power control........................................................ 58 9.1.11 Power supply de-coupling .................................................................... 59 9.1.12 Wi-Fi wireless disable and HW RF-KILL .................................................. 59 9.1.13 M.2 Bluetooth HW RF-KILL ................................................................... 59 9.1.14 BIOS ................................................................................................. 59 Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1–1 2–1 2–2 3–1 4–1 4–2 4–3 4–4 9–1 9–2 9–3 9–4 9–5 9–6 Figure 9–7 Jefferson Peak module block diagram ................................................................... 9 CNVi architecture ..............................................................................................11 Jefferson Peak interfaces ...................................................................................12 Power supply rise flow .......................................................................................24 Jefferson Peak M.2 2230 SKU dimensions ............................................................26 Jefferson Peak M.2 2230 SKU antenna configuration .............................................27 Jefferson Peak M.2 1216 SKU dimensions ............................................................28 Retention of M.2 cables .....................................................................................29 Platform connections to CNVi – Hybrid Key E scheme ............................................47 2230 Hybrid Key E socket pinout (names refer to platform socket side) ...................48 SD-1216 module pad-out for supporting CNVi and Discrete 1216 modules ...............52 SD-1216 module pad-out for supporting CNVi and Discrete 1216 modules ...............53 Board layout example showing breakout from JfP 1216 pads (design for CNVi only) ..54 Board layout example showing breakout from JfP 1216 pads (dual design for CNVi and discrete) ..........................................................................................................55 Coexistence UART for connectivity/modem 3-way configuration ..............................58 Tables Table Table Table Table Table Table Table Table Table Table Table Table 1-1 1-2 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 5–1 5–2 Key features (when connected to the MAC part residing in the SoC) ......................... 8 Jefferson Peak module SKUs ..............................................................................10 Hybrid Key E 2230-platform module pinout ..........................................................14 1216-platform module pinout (M.2 revision for 2015)............................................17 Input/Output electrical specifications ...................................................................22 Peak current consumption..................................................................................24 M.2 power supply and ripple limits ......................................................................25 Weight ...........................................................................................................26 Type 2230 antenna connector functionality ..........................................................26 Type 1216 antenna connector functionality ..........................................................29 Wi-Fi power consumption...................................................................................30 BT power consumption ......................................................................................31 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential April 2017 Document Number: 567240–1.0 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 5–3 5–4 5–5 5–6 5–7 5-8 6–1 6–2 6–3 7–1 7–2 7–3 7–4 7–5 7–6 9–1 9–2 9–3 Tx power per MCS (TBD) ...................................................................................32 Wi-Fi sensitivity ................................................................................................36 Wi-Fi throughput ..............................................................................................37 Bluetooth Tx power (TBD)..................................................................................38 Bluetooth sensitivity (TBD) ................................................................................38 Bluetooth throughput targets .............................................................................39 Thermal dissipation ...........................................................................................40 Thermal management .......................................................................................40 Storage conditions ............................................................................................41 Output power restrictions, main geographies........................................................42 Wi-Fi safety and regulatory USA .........................................................................43 Wi-Fi safety and regulatory Europe .....................................................................43 Wi-Fi safety and regulatory Japan .......................................................................43 Wi-Fi safety and regulatory Australia/New Zealand ...............................................44 Wi-Fi safety and regulatory other geographies......................................................44 Hybrid Key E interface mapping for different connectivity cards ..............................51 Socket 1 pullups and pulldowns ..........................................................................55 CNVio recommended parameters ........................................................................57 April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential Revision History Revision Description Date 0.5 Initial release September 2016 1.0 Corrected errors in CNVio trace numbers on M.2 2230 (pins 21 and 23 swapped) April 2017 Changed interface name to CNVio on drawings and text Removed most of the SAR chapter (need to describe new DRS mechanism) Removed WiGig option Updated 3D drawings for 2230 and 1216 Updated drawing for MB layout examples (CNVi and Dual Design) Added KPIs: • Wi-Fi Power consumption • BT Power consumption • Wi-Fi TPT targets • Wi-Fi Sensitivity targets Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential April 2017 Document Number: 567240–1.0 Abbreviations Term Description CNVi Integrated connectivity solution CRF Companion RF chip/module of the CNVi SoC System on chip PCH Platform control hub Pulsar The integrated IP part of the CNVi JfP Jefferson Peak companion RF chip/module LTE Long-term evolution (a mobile phone standard) RGI Radio generic interface, between JfP and Pulsar BRI Bluetooth radio interface, between JfP and Pulsar Wi-Fi Wireless LAN BT Bluetooth OTP One-Time Programmable non-volatile memory LDO Low-Dropout Regulator I/O Input/Output GPIO General-Purpose Input/Output RTC Real-Time Clock DC Direct Current CNVio High-speed data interface for CNVi DPHY Differential PHY (high-speed serial bus) MIPI Mobile Industry Processor Interface RF Radio Frequency IOSF Intel On-chip System Fabric Coex Coexistence UART Universal Asynchronous Serial Bus I2C Inter-Integrated Circuit bus ISH Integrated Sensor Hub CLINK Control Link AMT Active Management Technology USB Universal Serial Bus April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential Introduction Introduction The Intel® Integrated Connectivity Wireless-AC 9560 (code name Jefferson Peak or JfP) is an M.2 connectivity RF companion module for notebooks, tablets, and PCs. When combined with the Intel SoC that supports Connectivity Integration (CNVi), it supports the following radio technologies: 802.11abgn+acR2 MIMO 2x2 Bluetooth® 5.0 The product is a highly-integrated solution; the silicon design is based on the 28 nm process, and has a new architecture that splits the Wi-Fi and BT radio blocks into an integrated MAC block (residing in the Intel SoC) and the PHY/RF block (residing in the RF companion module). This solution provides higher level of integration with Intel platforms, and a set of advanced capabilities. The Jefferson Peak family includes two products: • JfP 2 – a module with Wi-Fi-2x2 radio (2 Wi-Fi chains) and BT • JfP 1 – A module with Wi-Fi 1x1 radio (single chain) and BT. For further details about the 1x1 version, please refer to the JfP1 EPS. The product is designed to be part of the Intel® Cannon Lake and Gemini lake platforms, supporting Microsoft* Windows* Threshold version as well as the Google* Chrome* OS and Linux*. 1.1 Key features Table 1-1 Key features (when connected to the MAC part residing in the SoC) Feature Platform Jefferson Peak Cannon Lake Y, U, H, DT Gemini Lake Connected standby and traditional platform types Form Factor and SKUs M.2 2230 M.2 1216-soldered down module Wi-Fi High performance low power dual band 802.11acR2 2x2 Bluetooth Bluetooth* 5.0 Host Interfaces Wi-Fi: PCI based (Internal to the SoC) BT: USB based (Internal to the SoC), optional UART/I2S (Internal to the SoC) AMT: CLINK (Internal to the SoC) Interfaces to the SoC Wi-Fi: CNVio (Intel propietary bus inspired by the DPHY low power interface) BT: BRI asynchronous serial bus (Intel propietary) Control: RGI asynchronous serial bus (Intel propietary) Clock: Single-endded, 38.4MHz (These interfaces connect the RF companion module to the MAC part which is integrated into the Intel SoC) Wi-Fi Alliance certifications 802.11a/b/g/n/ac , WPA/2 Personal and Enterprise, WPS2, 802.11w, WMM, WMM-PS, WFD, Miracast, Passpoint R2, Voice Personal Wi-Fi-Bluetooth Coex MIMO TX/TX and Rx/Rx Concurrency Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential April 2017 Document Number: 567240–1.0 Introduction LTE Coex Real-Time and Non Real-Time, LTE filter (not supported by all SKUs, see SKU description below) Performance TX Burst, TCP packet reordering, MSIx for reduced multi-core CPU load vPro AMT 11.0 Miracast Smart SKU Dynamic Regulatory SKU enabling automatic channel map and output power changes depending on the regulations of the country where it is operating CNVi/Discrete auto-detect Supports auto-detection by the SoC and by BIOS Operating System Win8.1*, Windows 10*, Linux*, Chrome* NOTE: 1. This module must be used with an Intel SoC which supports Connectivity Integration (CNVi). 2. Additional future platform support is expected. 3. Real-time and Non Real-time LTE coexistence supported with Intel LTE 7362. Figure 1–1 depicts the Jefferson Peak architecture. Figure 1–1 Jefferson Peak module block diagram SOC BT_RFKILL (W_Disable2#) Jefferson Peak Si Pulsar ISH LTE 7260 MFUART CPU I2S Internal PCI AUX Bus AUX Bus Coex MAC Shared Resources Mail Box SCU Coex Diplexe 2.4GHz 5GHz WLAN WLAN Internal CLINK 2.4G BPF PHY MAC USB2.0 FS POR BT BRI BT HS-UART Shared Resources Security Engine OTP Debug Sensors PHY 2.4GHz 5GHz 2.4G BPF Diplexe SCU CGU CGU POR 38.4 Mhz XTAL 32KHz DC2DC 3.3v BT_RFKILL (W_Disable2#) WiFi_RFKILL (W_Disable1#) WiFi_LED BT_LED NOTE: 2.4GHz band pass filters (BAW) for LTE coex will be supported on specific HW SKUs. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential Introduction 1.2 Jefferson Peak module SKUs The Jefferson Peak module supports the HW SKUs listed in Table 1-2. Table 1-2 Jefferson Peak module SKUs SKU Name Form Factor vPro Options LTE Coex Options JfP1 2230 2230 Hybrid Key E S3 Non vPRO No LTE coex JfP1-SD 1216 S3 Non vPRO No LTE coex JfP2 2230 2230 Hybrid Key E S3 vPRO/Non vPRO With LTE coex/ Without LTE coex JfP2-SD 1216 S3 vPRO/Non vPRO With LTE coex/ Without LTE coex Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 10 Intel Confidential April 2017 Document Number: 567240–1.0 Product Architecture Product Architecture 2.1 Integrated Connectivity concept 2.1.1 MAC-PHY split Integrated Connectivity (CNVi) is a new architecture for wireless connectivity devices. The concept of CNVi is to move a large part of the functional content of the connectivity chip from the radio chip into the Intel SoC. As a result, a large portion of the chip logic and memory resources is moved out of the radio chip while reducing the platform’s bill of material (BOM) size and cost. In the CNVi architecture, the MAC components of the Wi-Fi and Bluetooth cores, including processors, logic, and memory, are relocated from the radio chip into the SoC chip. Signal processing, analog and RF functions stay in the radio chip, which is called a Companion RF (CRF) chip or module in CNVi terminology. The part of the connectivity chip that is ported into the SoC is called Pulsar. Pulsar interfaces with the rest of the SoC functions through SoC-internal interfaces and busses, and does not require any external host interfaces at the platform level. On the other hand, interfacing Pulsar with the CRF module does require platform signals to be routed between the SoC and the CRF module. The CNVi architecture and the MAC-PHY split is shown in Figure 2–1. The integrated connectivity architecture places the MAC component of the Wi-Fi and BT cores inside the SoC. As a result, the host interfaces of Wi-Fi and BT are no longer part of the M.2 module, which is a Companion RF module. These host interfaces reside in the SoC and are not exposed to the platform. Figure 2–1 CNVi architecture M.2 pins SOC PCH resources (Power, I/O Chassis) Platform power GPIOs (RGI/BRI), clocks Pulsar CNVio CRF Module WiFi/BT PHY/RF Platform power 2.1.2 SoC and Companion RF compatibility In order to use the integrated connectivity architecture, the platform needs to include both an SoC and a connectivity device which supports CNVi. This means that the SoC needs to have the Pulsar block integrated, and a Companion RF module should be used in the design. The Jefferson Peak Companion RF module can support the following Intel SoC devices, which include Pulsar: • Cannon Lake PCH-LP • Cannon Lake PCH-H • Gemini Lake April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 11 Product Architecture 2.1.3 Swappable Companion RF/Discrete Companion RF (CRF) M.2 modules are swappable with discrete connectivity M.2 modules. The meaning of swappable in this context is that the design of the M.2 socket on the platform can allow using the same M.2 socket for both CNVi and discrete connectivity without the need to change the hardware configuration. When designing the platform to support swappable CRF/discrete, a CRF module can be changed to a discrete module, and vice versa, by simply removing one M.2 card type from the socket and swapping it with a new card type. Note that M.2 does not support hot-swapping and therefore the platform power should be turned off before doing this operation. The swappable concept is also applicable to 1216 soldered-down versions of the CRF, which also allows the same PCB design to have a single footprint supporting either a 1216-SD JfP CRF or a standard M.2 1216 discrete (not integrated) module. Obviously, in the soldered-down case, swapping modules will require disassembling the soldered module from the board. In order to design the platform to support both discrete and CNVi, and have the swappable feature, the platform needs to be designed properly. The specific guidelines for this type of design will be shown in the platform design guidelines section of this document. 2.2 Jefferson Peak interfaces The Jefferson Peak interfaces are illustrated in Figure 2–2. Figure 2–2 Jefferson Peak interfaces LTE Modem Power COEX 3.3V PCH 32KHz Clock RGI BRI CNVio Pulsar CRF CNVio 38.4Mhz clock CLK REQ RESET Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 12 Intel Confidential LED1/2 RF_KILL1/2 April 2017 Document Number: 567240–1.0 Product Architecture The Jefferson Peak M.2 module interfaces the platform and the SoC through a proprietary interface for CNVi. This interface connects between the JfP module and the SoC and between the JfP module and the platform. A high-level description of the interface is shown in Figure 2–2. Power supply The Jefferson peak module is powered by a 3.3V supply connected to the dedicated power pins on the M.2 module connector. Proper decoupling capacitors are required to be placed close to the module/socket pins. See more details in Section 1.1.1. 32KHz clock The Jefferson Peak module requires a slow (low power) clock to be supplied at the dedicated M.2 pins. This clock is normally generated by the SoC and routed between the SoC and the M.2 module. The clock rate is 32KHz and the signal is a standard logic level (either 3.3V or 1.8V can be used). BRI/RGI These are two serial asynchronous busses used for BT traffic (BRI) and for control data (RGI). Each bus has one signal per direction. The BRI and RGI busses do not require any clock to be sent with the data lines as the clock at the receiving end of the bus is extracted from the data itself. The BRI and RGI toggle at 76.4Mbouds each (full duplex). The signals are standard 1.8V logic level. The BRI and RGI do not need any pull-up resistors on the board. CNVio The CNVio signals connect the JfP module and the SoC. They are used as the main data bus for Wi-Fi, to transfer data between the Pulsar and the RF companion chip. The CNVio signals are PHYsically similar to the MIPI DPHY standard, but have a different (and Intel-proprietary) protocol. The CNVio bus has two data lanes and one clock for each direction. Both data and clock signals are differential, 100-Ohm signals. The total number of signals for the interface is 12 (6 pairs, 3 per direction). These signals should be routed as differential, controlled impedance traces. Due to the sensitivity of the CNVio bus to signal impairments, RF layout techniques and good length matching shall be used. Section 9.1.9.1 contains specific design guidelines for the CNVio routing. Reference clock (38.4MHz) This is the main clock used for both Pulsar (the MAC part which is inside the SoC) and Jefferson Peak. The clock is driven by the JfP output clock buffer at voltage levels of 1V (pk-pk). This clock shall be routed from JfP to the SoC with special care to minimize clock jitter. Section 9.1.9.3 contains specific design guidelines for the reference clock routing. Reset and Clock Request The Reset and Clock Request signals are automatically driven by the SoC to control the operation of the Companion RF and minimize system power consumption. The SoC uses the Reset only at initial power up. The Clock Request signal is used to change the Jefferson Peak power modes between highpower clock and low-power clock (per the system power states). LEDs Jefferson Peak M.2 module supports driving two LEDs to indicate wireless activity. These pins have open-drain buffers which sinks current (logical zero) when the LED is turned on. RF-KILL Jefferson Peak M.2 module SKUs support wireless disable (RF-KILL) command through the two RFKILL pins for turning off Wi-Fi and BT respectively. These pins can be connected to a platform switch or SoC GPIOs. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 13 Electrical Specifications Electrical Specifications This section provides information about the electrical specifications of the Jefferson Peak module. The specifications cover the module hardware interface signals. 3.1 2230 and 1216 form factor pinouts There are two pinout lists, one for the platform side, and one for the module side. Note that some signals are crossed (such as UART Rx on platform side is connected to TX on the module side). The 2230 module pinout is based on the Hybrid Key E scheme. The Hybrid Key E is an Intel-proprietary scheme, which is based on the mechanical and electrical specifications of the PCIe M.2 Electromechanical Spec, modified by changes to the pinout in order to support Intel’s Integrated Connectivity (CNVi). Note: Table 3-1 Hybrid Key E 2230-platform module pinout Pin Pin Name Platform Pinout Pin Name Module Pinout GND GND 3.3 V 3.3 V USB_D+ NC Direction w/respect to JfP Module JfP Voltage on Module Side 3.3 V IO 3.3 V Connection on Platform/Usage 3.3 V Supply Not used by Jefferson Peak Shall be connected to USB for supporting discrete module 3.3 V 3.3 V USB_D- NC 3.3 V IO 3.3 V 3.3 V Supply Not used by Jefferson Peak Shall be connected to USB for supporting discrete module LED1# LED1# GND GND PCM_CLK/I2S SCK NC WGR_D1N WGR_D1N CNVio PHY 10 PCM_SYNC/I2S WS/RF_RESET _B RF_RESET_B 1.8 V 11 WGR_D1P WGR_D1P CNVio PHY 12 PCM_IN/I2S SD_IN NC 1.8 V 13 GND GND 14 PCM_OUT/I2S SD_OUT/CLKR EQ0 CLKREQ0 WGR_D0N WGR_D0N 15 OD IO 1.8 V Wi-Fi LED Not used by Jefferson Peak Optional PCM interface for supporting discrete module CNVio bus RX lane 1 Jefferson peak RF (active low) Optional PCM interface for supporting discrete module CNVio bus RX lane 1 Not used by Jefferson Peak Optional PCM interface for supporting discrete module 1.8 V Clock request for the 38.4MHz clock (CNVi reference clock) Optional PCM interface for supporting discrete module CNVio PHY Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 14 Intel Confidential CNVio bus RX lane 0 April 2017 Document Number: 567240–1.0 Electrical Specifications Pin Pin Name Platform Pinout Pin Name Module Pinout Direction w/respect to JfP Module JfP Voltage on Module Side 16 LED2# LED2# OD 17 WGR_D0P WGR_D0P CNVio PHY 18 GND LNA_EN 19 GND GND 20 UART WAKE# NC Connection on Platform/Usage BT LED CNVio bus RX lane 0 This a special purpose test pin of the JfP module. Should be connected to Ground on the platform. 3.3 V Not used by Jefferson Peak Optional PCM interface for supporting discrete module 21 WGR_CLKN WGR_ CLKN CNVio PHY 22 UART RXD/BRI_RSP BRI_RSP 1.8 V 23 WGR_CLKP WGR_ CLKP 24 Connector Key Module Key 25 Connector Key Module Key 26 Connector Key Module Key 27 Connector Key Module Key 28 Connector Key Module Key 29 Connector Key Module Key 30 Connector Key Module Key 31 Connector Key Module Key 32 UART TXD/RGI_DT RGI_DT 33 GND GND 34 UART CTS/RGI_RSP RGI_RSP PETp0 NC 35 CNVio bus RX clock BRI bus RX Optional PCM interface for supporting discrete module CNVio PHY 1.8 V CNVio bus RX clock BRI bus TX Optional PCM interface for supporting discrete module 1.8 V RGI bus RX Optional PCM interface for supporting discrete module PCIe PHY Not used by Jefferson Peak Shall be connected to PCIe for supporting discrete module 36 UART RTS/BRI_DT BRI_DT 37 PETn0 NC 1.8 V PCIe PHY BRI bus TX Not used by Jefferson Peak Shall be connected to PCIe for supporting discrete module 38 CLINK RESET NC Not used by Jefferson Peak Optional CLINK interface for supporting discrete module 39 GND GND April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 15 Electrical Specifications Pin Pin Name Platform Pinout Pin Name Module Pinout 40 CLINK DATA NC Direction w/respect to JfP Module JfP Voltage on Module Side Connection on Platform/Usage Not used by Jefferson Peak Optional CLINK interface for supporting discrete module 41 PERp0 NC PCIe PHY Not used by Jefferson Peak Shall be connected to PCIe for supporting discrete module 42 CLINK CLK NC Not used by Jefferson Peak Optional CLINK interface for supporting discrete module 43 PERn0 NC PCIe PHY Not used by Jefferson Peak Shall be connected to PCIe for supporting discrete module 44 COEX3 (I/O) NC Not used by Jefferson Peak Optional Coex interface with LTE modem for supporting discrete module. See more details in Section 9.1.9.4 45 GND 46 COEX2 GND Not used by Jefferson Peak Optional Coex interface with LTE modem for supporting discrete module. See more details in Section 9.1.9.4 47 REFCLKP0 NC PCIe PHY Not used by Jefferson Peak Shall be connected to PCIe for supporting discrete module. 48 COEX1 NC Not used by Jefferson Peak Optional Coex interface with LTE modem when used with Discrete. See more details in Section 9.1.9.4 49 REFCLKN0 NC PCIe PHY Not used by Jefferson Peak Shall be connected to PCIe for supporting discrete module. 50 SUSCLK (32 kHz) C_P32K (32 kHz) 51 GND GND 52 PERST0# NC 3.3 V JfP also supports 1.8 V electrical levels on this signal 3.3 V Not used by Jefferson Peak Shall be connected to PCIe for supporting discrete module. 53 CLKREQ0# NC 3.3 V PCIe clock request. Not used by Jefferson Peak. Shall be connected to PCIe PCIe for supporting discrete module. 54 W_DISABLE2# W_DISABLE2# 55 PEWAKE0# NC 3.3 V JfP also supports 1.8 V electrical levels on this signal 3.3 V Not used by Jefferson Peak Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 16 Intel Confidential April 2017 Document Number: 567240–1.0 Electrical Specifications Pin Pin Name Platform Pinout Pin Name Module Pinout Direction w/respect to JfP Module JfP Voltage on Module Side Connection on Platform/Usage Shall be connected to PCIe PCIe for supporting discrete module. 56 W_DISABLE1# W_DISABLE1# 57 GND GND 58 I2C DATA/ A4WP_I2C_DA TA 59 3.3 V JfP also supports 1.8 V electrical levels on this signal NC 1.8 V Not used by Jefferson Peak. WT_D1N WT_D1N CNVio PHY 60 I2C CLK/ A4WP_I2C_CL NC 1.8 V 61 WT_D1P WT_D1P 62 ALERT#/ A4WP_IRQ# NC 63 GND GND 64 REFCLK0 REFCLK0 1V 65 WT_D0N WT_D0N CNVio PHY 66 PERST1# NC 67 WT_D0P WT_D0P 68 CLKREQ1# NC 69 GND GND 70 UIM_POWER_ SRC/GPIO1/ PEWAKE1# NA 71 WT_CLKN WT_ CLKN 72 3.3 V 3.3 V 73 WT_ CLKP WT_ CLKP 74 3.3 V 3.3 V 75 GND GND Table 3-2 CNVio bus TX lane 1 Not used by Jefferson Peak. CNVio PHY 1.8 V CNVio bus TX lane 1 Not used by Jefferson Peak 38.4MHz clock from the JfP Module to the SoC CNVio bus TX lane 0 Not used by Jefferson Peak CNVio PHY CNVio bus TX lane 0 Not used by Jefferson Peak Not used by Jefferson Peak CNVio PHY CNVio bus TX clock 3.3 V Supply CNVio PHY CNVio bus TX clock 3.3 V Supply 1216-platform module pinout (M.2 revision for 2015) Pin # Pin name Function when CNVi is used Function when Standard (discrete) M.2 is used UIM_POWER_SRC/GPIO1 Not used UIM_POWER_SRC/GPIO1 UIM_POWER_SNK Not used UIM_POWER_SNK UIM_SWP Not used UIM_SWP 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V April 2017 Document Number: 567240–1.0 Comments Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 17 Electrical Specifications Pin # Pin name Function when CNVi is used Function when Standard (discrete) M.2 is used GND GND GND RESERVED Not used RESERVED ALERT# Not used ALERT# I2C_CLK Not used I2C_CLK 10 I2C_DATA Not used I2C_DATA 11 COEX_TXD Not used COEX_TXD 12 COEX_RXD Not used COEX_RXD 13 COEX3 Not used COEX3 14 SYSCLK/GNSS0 Not used SYSCLK/GNSS0 15 TX_BLANKING/GNSS1 Not used TX_BLANKING/GNSS1 16 RESERVED Not used RESERVED 17 GND GND GND 18 RESERVED Not used Not used 19 RESERVED Not used Not used 20 GND GND GND 21 RESERVED Not used Not used 22 RESERVED Not used Not used 23 GND GND GND 24 RESERVED Not used Not used 25 RESERVED Not used Not used 26 GND GND GND 27 SUSCLK(32kHz)(3.3V) 32KHz clock (3.3V) SUSCLK(32kHz)(3.3V) 28 W_DISABLE1# W_DISABLE1# W_DISABLE1# 29 PEWAKE# Not used PEWAKE# 30 CLKREQ# Not used CLKREQ# 31 PERST# Not used PERST# 32 GND GND GND 33 REFCLKN0 Not used REFCLKN0 34 REFCLKP0 Not used REFCLKP0 35 GND GND GND 36 PERn0 Not used PERn0 37 PERp0 Not used PERp0 38 GND GND GND 39 PETn0 Not used PETn0 40 PETp0 Not used PETp0 41 GND GND GND Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 18 Intel Confidential Comments Can be shorted to A27 on the Motherboard April 2017 Document Number: 567240–1.0 Electrical Specifications Pin # Pin name Function when CNVi is used Function when Standard (discrete) M.2 is used 42 CLink_CLK Not used CLink_CLK 43 CLink_DATA Not used CLink_DATA 44 CLink_RESET Not used CLink_RESET 45 SDIO_RESET# Not used Not used SDIO is not supported 46 SDIO_WAKE# Not used Not used SDIO is not supported 47 SDIO_DATA3 Not used Not used SDIO is not supported 48 SDIO_DATA2 Not used Not used SDIO is not supported 49 SDIO_DATA1 Not used Not used SDIO is not supported 50 SDIO_DATA0 Not used Not used SDIO is not supported 51 SDIO_CMD Not used Not used SDIO is not supported 52 SDIO_CLK Not used Not used SDIO is not supported 53 UART_WAKE# (3.3V) Not used UART_WAKE# (3.3V) 54 LPSS_UART_RTS/bri_dt Not used LPSS_UART_RTS/bri_dt Can be shorted to A38 on the Motherboard 55 LPSS_UART_RXD/bri_rsp Not used LPSS_UART_RXD/bri_rsp Can be shorted to A39 on the Motherboard 56 LPSS_UART_TXD/rgi_dt Not used LPSS_UART_TXD/rgi_dt Can be shorted to A40 on the Motherboard 57 LPSS_UART_CTS/rgi_rsp Not used LPSS_UART_CTS/rgi_rsp Can be shorted to A41 on the Motherboard 58 PCM_SYNC/I2S_WS Not used PCM_SYNC/I2S_WS Can be shorted to A42 on the Motherboard 59 PCM_OUT/I2S_SD_OUT Not used PCM_OUT/I2S_SD_OUT Can be shorted to A43 on the Motherboard 60 PCM_IN/I2S_SD_IN Not used PCM_IN/I2S_SD_IN 61 PCM_CLK/I2S_SCK Not used PCM_CLK/I2S_SCK 62 GND GND GND 63 W_DISABLE2# W_DISABLE2# W_DISABLE2# 64 LED2# LED2# LED2# 65 LED1# LED1# LED1# 66 RESERVED Not used RESERVED 67 RESERVED Not used RESERVED 68 GND GND GND 69 USB_D- Not used USB_D- 70 USB_D+ Not used USB_D+ 71 GND GND GND 72 3.3V 3.3V 3.3V 73 3.3V 3.3V 3.3V 74 GND GND GND April 2017 Document Number: 567240–1.0 Comments Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 19 Electrical Specifications Pin # Pin name Function when CNVi is used Function when Standard (discrete) M.2 is used 75 GND GND GND 76 GND GND GND 77 GND GND GND 78 GND GND GND 79 GND GND GND 80 GND GND GND 81 GND GND GND 82 GND GND GND 83 GND GND GND 84 GND GND GND 85 GND GND GND 86 GND GND GND 87 GND GND GND 88 GND GND GND 89 GND GND GND 90 GND GND GND 91 GND GND GND 92 GND GND GND 93 GND GND GND 94 GND GND GND 95 GND GND GND 96 GND GND GND G1 GND GND GND G2 GND GND GND G3 GND GND GND G4 GND GND GND G5 GND GND GND Thermal pad G6 GND GND GND Thermal pad G7 GND GND GND Thermal pad G8 GND GND GND Thermal pad G9 GND GND GND Thermal pad G10 GND GND GND Thermal pad G11 GND GND GND Thermal pad G12 GND GND GND Thermal pad A07 GND GND Not Applicable A08 A4WP_IRQ# NC Not Applicable Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 20 Intel Confidential Comments Not connected April 2017 Document Number: 567240–1.0 Electrical Specifications Pin # Pin name Function when CNVi is used Function when Standard (discrete) M.2 is used A09 A4WP_CLK NC Not Applicable Not connected A10 A4WP_DATA NC Not Applicable Not connected A11 RESERVED RESERVED Not Applicable Not connected A12 RESERVED RESERVED Not Applicable Not connected A13 RESERVED RESERVED Not Applicable Not connected A14 RESERVED RESERVED Not Applicable Not connected A15 LNA_EN GND Not Applicable Connect to GND A16 RESERVED RESERVED Not Applicable Not connected A17 RESERVED RESERVED Not Applicable Not connected A18 RESERVED RESERVED Not Applicable Not connected A19 WT_CLKP WT_CLKP Not Applicable A20 WT_CLKN WT_CLKN Not Applicable A21 WT_D0P WT_D0P Not Applicable A22 WT_D0N WT_D0N Not Applicable A23 WT_D1P WT_D1P Not Applicable A24 WT_D1N WT_D1N Not Applicable A25 C_P32K C_P32K Not Applicable A26 GND GND Not Applicable A27 RESERVED RESERVED Not Applicable Not connected A28 RESERVED RESERVED Not Applicable Not connected A29 RESERVED RESERVED Not Applicable Not connected A30 RESERVED RESERVED Not Applicable Not connected A31 GND GND Not Applicable A32 WGR_CLKP WGR_CLKP Not Applicable A33 WGR_CLKN WGR_CLKN Not Applicable A34 WGR_D0P WGR_D0P Not Applicable A35 WGR_D0N WGR_D0N Not Applicable A36 WGR_D1P WGR_D1P Not Applicable A37 WGR_D1N WGR_D1N Not Applicable A38 BRI_DT BRI_DT Not Applicable Can be connected to 54 on the Motherboard A39 BRI_RSP BRI_RSP Not Applicable Can be connected to 55 on the Motherboard A40 RGI_DT RGI_DT Not Applicable Can be connected to 56 on the Motherboard A41 RGI_RSP RGI_RSP Not Applicable Can be connected to 57 on the Motherboard April 2017 Document Number: 567240–1.0 Comments Can be connected to 27 on the Motherboard Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 21 Electrical Specifications Pin # Pin name Function when CNVi is used Function when Standard (discrete) M.2 is used A42 RF_RESET_B RF_RESET_B Not Applicable Can be connected to 58 on the Motherboard A43 CLKREQ0 CLKREQ0 Not Applicable Can be connected to 59 on the Motherboard A44 REFCLK0 REFCLK0 Not Applicable A45 NO CONNECT NO CONNECT Not Applicable Pin must be left floating A46 RESERVED RESERVED Not Applicable Not connected A47 RESERVED RESERVED Not Applicable Not connected A48 3.3V 3.3V Not Applicable A49 3.3V 3.3V Not Applicable A50 GND GND Not Applicable 3.2 Input/output electrical specifications Table 3-3 Input/Output electrical specifications I/O type 1.8V I/O RF_RESET_B Symbol Parameter Min Max Unit Comments Notes VIH Input High Voltage 1.26 2.1 VIL Input Low Voltage -0.3 0.54 RPU/PD Weak Pull-Up or PullDown 70 150 Kohm IIN Input Leakage Current 10 uA No Pull Up/Down VOH Output High Voltage 1.8 Io = 2mA 1.62 Load = 20pF VOL Output Low Voltage 0.18 Io = 2mA Load = 20pF 1.8V FS I/O A4WP_IRQ# TR, TF Rise, Fall Time ns CIO IO Pin Capacitance pF VIH Input High Voltage 1.26 2.1 VIL Input Low Voltage -0.3 0.54 RPU/PD Weak Pull-Up or PullDown 100 180 Kohm IIN Input Leakage Current 10 uA VOL Output Low Voltage Push-Pull Push-pull VOH Output Low Voltage Push-Pull Push-pull TR, TF Rise, Fall Time Push-Pull Push-pull A4WP_I2C_CLK A4WP_I2C_CLK (Note 1) 0.36 Load = 20pF No Pulls Io = 2mA Load = 50pF 1.62 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 22 Intel Confidential 1.8 Io = 2mA Load = 50pF 18.5 ns Load = 50pF April 2017 Document Number: 567240–1.0 Electrical Specifications I/O type Symbol VOL Parameter Output Low Voltage Min Max Unit 0.36 Io = 2mA Open Drain 1.8V FS_CR CLKREQ0 Notes Load = 64pF RPU = 1Kohm CIO IO Pin Capacitance pF VIH Input High Voltage 1.26 2.1 VIL Input Low Voltage -0.3 0.54 RPU/PD Weak Pull-Up or PullDown 100 180 Kohm IIN Input Leakage Current 10 uA No Pulls VOH Output High Voltage 1.8 Io = 2mA (Note 2) 1.62 Load = 20pF VOL Output Low Voltage 0.18 Io = 2mA Load = 20pF 1.8V FS_3VT C_P32K TR, TF Rise, Fall Time 18.5 ns CIO IO Pin Capacitance pF VIH Input High Voltage 1.26 2.1 VIL Input Low Voltage -0.3 0.54 RPU/PD Weak Pull-Up or PullDown 150 (typical) IIN Input Leakage Current VOH Output High Voltage (Note 3) 1.62 Load = 20pF Kohm 10 uA No Pulls 1.8 Io = 1mA Load = 30pF VOL Output Low Voltage 0.18 Io = 1mA Load = 30pF BRI and RGI 1.8V I/O TR, TF Rise, Fall Time 20 ns CIO IO Pin Capacitance pF VIH Input High Voltage 1.26 TBD VIL Input Low Voltage TBD 0.54 BRI_DT RPU/PD BRI_RSP IIN RGI_DT VOH Output High Voltage 1.62 1.8 RGI_RSP VOL Output Low Voltage 0.18 (Note 4) TR, TF Rise, Fall Time 1.5 4.5 ns Rb Baud rate 4.8 76.8 Mbaud CIO IO Pin Capacitance pF CNVio Load = 30pF 50ohm driver impedance Load = 35pF Tolerance +/-5% Signal parameters follow the MIPI D-PHY Specifications Rev1.1 (Note 5) April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 23 Electrical Specifications NOTES: 1. I2C max speed will be 1MHz (Fast plus Mode). I2C SDA & SCL I/Os must comply with 120ns max rise/fall time. I/O are protected against back-bias up to 1.8V and can withstand I/O voltage when the power supply is off. 2. I/O are protected against back-bias up to 1.98V and can withstand I/O voltage when the power supply is off. 3. Input is 3.6V tolerant. I/O are protected against back-bias up to 3.6V and can withstand I/O voltage when the power supply is off. 4. I/O are protected against back-bias up to 1.98V and can withstand I/O voltage when the power supply is off. 5. The D-PHY I/O pins must comply with the DC electrical specifications in “MIPI Alliance Specification for D-PHY Rev1.1.” Specifically, the D-PHY JfP transmitter (JfP to Pulsar) DC characteristics are found in Section 9.1, Table 16. The D-PHY JfP receiver (Pulsar to JfP) DC characteristics are found in Section 9.2, Table 20. 3.3 Peak current consumption Table 3-4 Peak current consumption Name Description Peak current Peak current from 3.3 V supply 3.4 Value [mA] Notes 1360 M.2 power and ripple limits The supply voltage rise should be continuous and with a max rise time of 10mSec (0 V to 3.3 V). It should not have any glitches or steps. Figure 3–1 shows examples of wrongful and correct power up schemes. Figure 3–1 Power supply rise flow 3.4.1 √ Power supply ripples There must not be any glitches on the power supply that dip more 0.3 V. Any glitch that is higher than 0.3V may be interpreted by the module as a power-on reset, which will cause the module to lose stored data and reboot. During platform low-power modes, such as S3 (stand-by state), glitches will lead to connection failure. Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 24 Intel Confidential April 2017 Document Number: 567240–1.0 Electrical Specifications Table 3-5 M.2 power supply and ripple limits Platform Power Rail Requirements Power supply voltage range 3.3 V +/–0.165 V Power on rise time <10 msec Maximum ripple 200 mVPP, frequency 10–500 kHz Allowed power rail noise 300 mVpp 3.4.2 Platform state transitions Platform designers should carefully design the transition from platform on state to platform stand-by state and vice versa, so that the power supply will remain stable and have no glitches. 3.5 M.2 ground (GND) All ground pins are connected on the M.2 module to a common ground plane. The platform designer should connect all M.2 GND pins to the platform system GND. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 25 Mechanical Specifications Note: Mechanical Specifications The module’s mechanical specifications adhere to the PCIe_M.2_Electromechanical_Spec. 4.1 Weight Table 4-1 Weight Product SKU Size (mm × mm) Weight (g) Jefferson Peak 2230 22x30 TBD Jefferson Peak 1216 12x16 TBD 4.2 M.2 2230 mechanical specification This section describes the mechanical specification of Jefferson Peak 2230 modules. Figure 4–1 shows the dimensions for type 2230. Antenna connector configuration and functionality for this form factor is listed in Table 4-2 and shown in Figure 4–2 Figure 4–1 Jefferson Peak M.2 2230 SKU dimensions Table 4-2 Type 2230 antenna connector functionality Antenna connector functionality Wi-Fi (Chain A) + BT ANT1 Wi-Fi (Chain B) ANT2 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 26 Intel Confidential April 2017 Document Number: 567240–1.0 Mechanical Specifications Figure 4–2 Jefferson Peak M.2 2230 SKU antenna configuration 4.3 M.2 1216 mechanical specification This section describes the mechanical specification of Jefferson Peak 2230 modules. Figure 4–3 shows the dimensions for type 1216. Antenna connector configuration and functionality for this form factor is listed in Table 4-3 and shown in Figure 4–3. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 27 Mechanical Specifications Figure 4–3 Jefferson Peak M.2 1216 SKU dimensions Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 28 Intel Confidential April 2017 Document Number: 567240–1.0 Mechanical Specifications Antenna connector functional allocation for this form factor is defined as shown in Table 4-3 (note the functionality is vendor-defined according to the M.2 spec). Note: In Jefferson Peak 1216, antenna ANT2 is not present. Table 4-3 Type 1216 antenna connector functionality Antenna connector functionality Wi-Fi (Chain A) + BT ANT1 Wi-Fi (Chain B) ANT3 4.4 Z height Jefferson Peak supports S3 Z-height module (1.5 mm from module surface to the top of the shield). 4.5 M.2 antenna retention 4.5.1 Recommended method for retention of M.2 cable It is recommended to restrain the antenna cables of M.2 products within the first 25 mm or less of cable length, leaving the RF connectors on the module. It is recommended to use a robust tape or adhesive to secure the cables so they do not move or pull on the RF connector during shock and vibration of the system, as shown in Figure 4–4. Figure 4–4 Retention of M.2 cables April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 29 Performance Performance 5.1 Power consumption 5.1.1 Wi-Fi power consumption Table 5–1 Wi-Fi power consumption Wi-Fi Power KPI JfP2 [mW] Unassociated 7.1 Idle associated 2.4GHz (consumer) DTIM=3 OOB Idle associated 5.2GHz (enterprise) DTIM=1 OOB 4.8 Idle associated 2.4GHz (consumer) DTIM=3 benchmark BT disabled No scan 3.5 Idle associated 5.2GHz (enterprise) DTIM=1 benchmark BT disabled No scan 4.1 Web Browsing 2.4GHz (consumer) 13 Web Browsing 5.2GHz (enterprise) 15 VOIP 2.4GHz (consumer) NDP 247 VOIP 5.2GHz (enterprise) NDP 300 Video Conference 2.4GHz (consumer) NDP 260 Video Conference 5.2GHz (enterprise) NDP 306 Video Streaming 2.4GHz (consumer) NDP 30 Video Streaming 5.2GHz (enterprise) NDP 36 TpT – 11n LB-20 Tx 11n 943 TpT – 11n LB-20 Rx 11n 404 TpT – 11n HB-40 Tx 11n 1050 TpT – 11n HB-40 Rx 11n 550 TpT – 11ac HB-80 Tx 11ac 970 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 30 Intel Confidential April 2017 Document Number: 567240–1.0 Performance TpT – 11ac HB-80 Rx 11ac 675 NOTES: 1. BT in SW RF-KILL in all the tests 2. HB values refer to internal FE SKU 3. OS: Win10 5.1.2 BT power consumption Table 5–2 BT power consumption BT Power KPI JfP2 [mW] Target eSCO 33.69 MP3 playback BT A2DP 34.97 Continuous TX 10dBm 163.75 Continuous RX 111.02 HID BLE connected idle 13.35 BLE advertising 2.04 BLE scanning 3.74 Page scan 5.73 Page and inquiry scan 7.84 BR/EDR sniff 5.92 OPP Tx 100.04 OPP Rx 101.71 NOTES: 1. Wi-Fi in SW RF-KILL in all the tests 2. OS: Win10 3. WsP is Master device April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 31 Performance 5.2 Wi-Fi performance 5.2.1 Wi-Fi Tx power (TBD) Note: The content in this section is to be determined (TBD) in the next release. Table 5–3 describes the device’s actual output power in various rates and channels, taking into account both Tx power regulatory limits and IEEE mask and EVM performance (the minimum between these). This is a change from previous generations of EPS documents. Please note that the numbers in Table 5–3 are for the default Tx numbers. Once location is determined, Tx power might increase on certain channels according to the regulatory rules in the specific country. Table 5–3 Tx power per MCS (TBD) JfP (2230/1216) CH MCS AC–9560 11b (CCK) 11g Tx Power 2230 MS (dBm, acc: +/–1 dB) Power Target Ch A Ch.1 11 Mbps Ch.2 11 Mbps Ch.3 11 Mbps Ch.4 11 Mbps Ch.5 11 Mbps Ch.6 11 Mbps Ch.7 11 Mbps Ch.8 11 Mbps Ch.9 11 Mbps Ch.10 11 Mbps Ch.11 11 Mbps Ch.12 11 Mbps Ch.13 11 Mbps Ch.1 6 Mbps Tx Power 1216 (dBm, acc: +/–1 dB) Power Target Ch B Power Target Ch A Power Target Ch B 54 Mbps Ch.2 6 Mbps 54 Mbps Ch.3 6 Mbps 54 Mbps Ch.4 6 Mbps 54 Mbps Ch.5 6 Mbps 54 Mbps Ch.6 6 Mbps 54 Mbps Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 32 Intel Confidential April 2017 Document Number: 567240–1.0 Performance JfP (2230/1216) CH MCS AC–9560 Tx Power 2230 MS (dBm, acc: +/–1 dB) Power Target Ch A Ch.7 Power Target Ch B Tx Power 1216 (dBm, acc: +/–1 dB) Power Target Ch A Power Target Ch B 6 Mbps 54 Mbps Ch.8 6 Mbps 54 Mbps Ch.9 6 Mbps 54 Mbps Ch.10 6 Mbps 54 Mbps Ch.11 6 Mbps 54 Mbps Ch.12 6 Mbps 54 Mbps Ch.13 6 Mbps 54 Mbps 11n Ch1 MCS7/ 20 MHz Ch2 MCS7/ 20 MHz Ch3 MCS7/ 20 MHz Ch.4 MCS7/ 20 MHz Ch.5 MCS7/ 20 MHz Ch.6 MCS7/ 20 MHz Ch.7 MCS7/ 20 MHz Ch.8 MCS7/ 20 MHz Ch.9 MCS7/ 20 MHz Ch.10 MCS7/ 20 MHz Ch.11 MCS7/ 20 MHz Ch.12 MCS7/ 20 MHz April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 33 Performance JfP (2230/1216) CH MCS AC–9560 11a Tx Power 2230 MS (dBm, acc: +/–1 dB) Power Target Ch A Ch.13 MCS7/ 20 MHz Ch.36 6 Mbps Tx Power 1216 (dBm, acc: +/–1 dB) Power Target Ch B Power Target Ch A Power Target Ch B 54 Mbps Ch.40 6 Mbps 54 Mbps Ch.44 6 Mbps 54 Mbps Ch.48 6 Mbps 54 Mbps Ch.52 6 Mbps 54 Mbps Ch.56 6 Mbps 54 Mbps Ch.60 6 Mbps 54 Mbps Ch.64 6 Mbps 54 Mbps Ch.100 6 Mbps 54 Mbps Ch.104 6 Mbps 54 Mbps Ch.157 6 Mbps 54 Mbps Ch.161 6 Mbps 54 Mbps Ch.165 6 Mbps 54 Mbps 11an Ch.36 MCS7/ 20 MHz Ch.38 MCS7/ 40 MHz Ch.40 MCS7/ 20 MHz Ch.46 MCS7/ 40 MHz Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 34 Intel Confidential April 2017 Document Number: 567240–1.0 Performance JfP (2230/1216) CH MCS AC–9560 11ac Tx Power 2230 MS (dBm, acc: +/–1 dB) Power Target Ch A Ch.100 MCS7/ 20 MHz Ch.102 MCS7/ 40 MHz Ch.161 MCS7/ 20 MHz Ch.159 MCS7/ 40 MHz Ch.165 MCS7/ 20 MHz Ch.40 MCS8/ 20 MHz Ch.46 MCS9/ 40 MHz Ch.42 MCS9/ 80 MHz Ch.100 MCS8/ 20 MHz Ch.102 MCS9/ 40 MHz Ch.106 MCS9/ 80 MHz Ch.161 MCS8/ 20 MHz Ch.159 MCS9/ 40 MHz Ch.155 MCS9/ 80 MHz Power Target Ch B Tx Power 1216 (dBm, acc: +/–1 dB) Power Target Ch A Power Target Ch B NOTES: 1. The TX power per MCS relate to IEEE, mask compliance and limited by regulatory TX power limits. 2. The values relate to internal FE SKU 3. The values are for typical device and typical conditions April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 35 Performance 5.2.2 Wi-Fi sensitivity Table 5–4 Wi-Fi sensitivity Wi-Fi Sensitivity Targets 2230 [dBm] Band Mode Conditions LB 11b CCK, Rate 1Mbps, BW 20MHz, 10% PER Typ Max Wi-Fi Sensitivity Targets 1216 [dBm] Typ Max -96.5 -96.5 -94.5 -94.5 Rate 54Mbps, BW 20 MHz, 10% PER -77.0 -77.0 MCS0, BW 20 MHz, 10% PER -94.5 -94.5 -76.5 -76.5 -92.0 -92.0 -74.0 -74.0 -94.0 -94.0 Rate 54Mbps ,20 MHz, 10% PER -76.5 -76.5 MCS0, BW 20 MHz, 10% PER -94.0 -94.0 -76.0 -76.0 -92.0 -92.0 -73.5 -73.5 MCS0 , BW 20 MHz, 10% PER -94.5 -94.5 MCS8, BW 20 MHz, 10% PER -72.5 -72.5 MCS0, BW 40 MHz, 10% PER -92.0 -92.0 MCS8 , BW 40 MHz, 10% PER -69.5 -69.5 MCS9, BW 40 MHz, 10% PER -68.0 -68.0 MCS0, BW 80 MHz, 10% PER -88.5 -88.5 CCK, Rate 11Mbps, BW 20MHz, 10% PER 11g Rate 6Mbps, BW 20MHz, 10% PER Rate 12Mbps, BW 20 MHz, 10% PER 11n MCS6, BW 20 MHz, 10% PER MCS7, BW 20 MHz, 10% PER MCS15, BW 20 MHz, 10% PER MCS0, BW 40 MHz, 10% PER MCS6, BW 40 MHz, 10% PER MCS7, BW 40 MHz, 10% PER MCS15, BW 40 MHz, 10% PER HB 11a Rate 6Mbps, BW 20 MHz, 10% PER Rate 12Mbps, 20 MHz, 10% PER 11n MCS6, BW 20 MHz, 10% PER MCS7 , BW 20 MHz, 10% PER MCS15 , BW 20 MHz, 10% PER MCS0, BW 40 MHz, 10% PER MCS6, BW 40 MHz, 10% PER MCS7, BW 40 MHz, 10% PER MCS15, BW 40 MHz, 10% PER 11ac MCS6, BW 80 MHz, 10% PER Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 36 Intel Confidential April 2017 Document Number: 567240–1.0 Performance Wi-Fi Sensitivity Targets 2230 [dBm] Band Mode Conditions Typ Wi-Fi Sensitivity Targets 1216 [dBm] Max Typ Max MCS7, BW 80 MHz, 10% PER MCS8, BW 80 MHz, 10% PER -66.5 -66.5 MCS9, BW 80 MHz, 10% PER -64.5 -64.5 MCS0, BW 160 MHz, 10% PER -85.5 -85.5 MCS8, BW 160 MHz, 10% PER -62.5 -62.5 MCS9, BW 160 MHz, 10% PER -60.5 -60.5 NOTES: 1. Measured at ANT port 2. Typical means Nominal corner, AVG over non BE CHs. AVG over freq segment and chains 3. Max means over PVT 5.2.3 Wi-Fi throughput targets Table 5–5 Wi-Fi throughput Scenario Description Value [Mbps] 11n 20 MHz 2SS Rx Conductive, best attenuation, UDP 124 11n 20 MHz 2SS TX Conductive, best attenuation, UDP 125 11n 40 MHz 2SS Rx Conductive, best attenuation, UDP 251 11n 40 MHz 2SS TX Conductive, best attenuation, UDP 248 11ac 80 MHz 2SS Rx Conductive, best attenuation, UDP 660 11ac 160 MHz 2SS TX Conductive, best attenuation, UDP 650 11ac 160 MHz 2SS Rx Conductive, best attenuation, UDP 1509 11ac 80 MHz 2SS TX Conductive, best attenuation, UDP/IP 1533 11n 20 MHz 2SS Rx Conductive, best attenuation, TCP/IP 120 11n 20 MHz 2SS TX Conductive, best attenuation, TCP/IP 112 11n 40 MHz 2SS Rx Conductive, best attenuation, TCP/IP 241 11n 40 MHz 2SS TX Conductive, best attenuation, TCP/IP 210 11ac 80 MHz 2SS Rx Conductive, best attenuation, TCP/IP 600 11ac 80 MHz 2SS TX Conductive, best attenuation, TCP/IP 575 11ac 160 MHz 2SS Rx Conductive, best attenuation, TCP/IP 1251 11ac 160 MHz 2SS TX Conductive, best attenuation, TCP/IP 1252 NOTE: Notes The throughput values relate to Intel® Skylake Platform and CPU, Single User. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 37 Performance 5.3 Bluetooth performance 5.3.1 Bluetooth Tx power (TBD) Note: The content in this section is to be determined (TBD) in the next release. Table 5–6 Bluetooth Tx power (TBD) WsP BT Tx power Tx Power 1216 (dBm, acc: +/–2 dB) Tx Power 2230 MS (dBm, acc: +/–2 dB) Notes BR Typical Conditions EDR2 Typical Conditions EDR3 Typical Conditions BLE Typical Conditions Typical Operating Conditions are defined as: 1. Temperature of 25°C and nominal supply voltage. 2. The measured material is of typical process only. 3. The reported figure is the average power level over the frequency band. 4. For all measurements, the specified temperature is measured at the shield. 5. The power levels are specified at the product antenna port. 6. Accuracy is +/-2dB. 5.3.2 Bluetooth sensitivity (TBD) Note: The content in this section is to be determined (TBD) in the next release. Table 5–7 Bluetooth sensitivity (TBD) WsP BT Tx power Tx Power 2230 MS (dBm, acc: +/–1.5 dB) Tx Power 1216 (dBm, acc: +/–1.5 dB) Notes BR Typical Conditions EDR2 Typical Conditions EDR3 Typical Conditions BLE Typical Conditions Typical Operating Conditions are defined as: 1. Nominal BQB test conditions. In addition the following definitions apply: 2. Temperature of 25°C and nominal supply voltage 3. The measured material is of typical process only 4. The measurements are performed at spectrally clean (i.e., non-spur) channels 5. For all measurements, the specified temperature is measured at the shield. 6. The sensitivity is specified at the product antenna port. 7. Assuming all co-located cores are disabled. 8. Averaged value across frequency Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 38 Intel Confidential April 2017 Document Number: 567240–1.0 Performance 5.3.3 Bluetooth throughput targets This section details the Bluetooth throughput. The values are applicable to both 2230 and 1216 form factors. OPP throughput testing occurs in fully conductive environment. BTOE is a Broadcom 2070 card in an Intel NUC. Size of the file transferred is 3 MB and is tested three (3) times at each point. Wi-Fi and other cores are disabled. Bluetooth is connectable, not discoverable. Table 5-8 Bluetooth throughput targets Test Type Attenuation TX OPP 25-60db RX OPP 25-60db April 2017 Document Number: 567240–1.0 Typical TPT [Kbps] Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 39 Thermal Specifications Note: 6.1 Thermal Specifications The numbers in this section are not final, and are subject to change. Thermal dissipation Maximum thermal dissipation is based on the assumption that both Wi-Fi and Bluetooth communication are active. Table 6–1 describes the thermal dissipation and targets per operated mode. Table 6–1 Thermal dissipation Use Case Wi-Fi BT Worst case TDP: Based on average power consumption measurement over five minutes with max TCP/IP throughput activity NA Note: PC (mW) Wi-Fi BT NA Not applicable for scenarios that may only be exercised using lab or OEM support software tools. 6.2 Thermal specifications Table 6–2 Thermal management Name Description Thermal shield performance targets Full performance at shield temperatures up to 80 ºC. Testing conditions: System environmental conditions: High limit: ~50 ºC (TBD) under controlled environment (oven), with no air flow (inside a box). Low limit: 0 ºC (starting point) under controlled environment (oven), with no air flow (inside a box). Thermal Silicon protection (CT–Kill) 6.3 Thermal silicon protection will not be activated below 85 ºC (TBD) T– shield temperature. Thermal management The device thermal management cuts off RF operation once a maximum temperature threshold (Critical Temperature termination, CT–Kill) has been exceeded. After the cutoff point is reached, the RF remains at the off state until it cools down to the thermal activation threshold. During this time the host cannot set the RF back to on. When the product is heating up and nearing CT Kill, it will start decreasing the Wi-Fi activity in order to prevent the unit from heating further and reaching critical temperature. In such case, connectivity will be maintained but performance might be degraded gradually. Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 40 Intel Confidential April 2017 Document Number: 567240–1.0 Thermal Specifications 6.4 Module placement recommendations The module disperses excess heat through the RF shield and the screws that ground the module to the chassis. Correct module placement will ensure optimal thermal performance: The 2230 module orientation should be shield up. The 2230 module connection to chassis should be with a single metal screw. 6.5 Nonoperational module thermal storage Table 6–3 Storage conditions Environment Limits Storage Temperature (Non–Operational) –40 ºC to 70 ºC Humidity (Non–Operational) 50% to 90% non–condensing (at temperatures of 25 ºC to 35 ºC) April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 41 Regulatory Regulatory 7.1 Regulatory channel support and output power Jefferson Peak provides regulatory compliance via statically-configured SKUs or DRS (Dynamic Regulatory Solution). For further details on the DRS scheme, refer to the DRS application note (see Section 8 8 ). 7.2 Wi-Fi channel configuration 7.2.1 Channel configuration – RF output power The values listed in Table 5–3 represent the target power for the calibration process without antennae gain. This value has been verified to ensure margin from the regulatory limit based on post EEPROM factory calibration measurements using a diagnostic tool that operates the WLAN card at a ~99% DC (Duty Cycle) taken on both the main and auxiliary antenna ports. As part of the factory test process, Intel measures the output power of every card. Any cards that exceed the maximum limits (EEPROM + 1 dB) will not pass the factory test. While in operation the card adjusts TX power using a closed loop TX power calibration algorithm. To do so, a power detector and temperature sensor are used. Intel uses the following antenna gain value for product and country certification work: 3 dBi for 2.4 GHz and 5 dBi for 5 GHz. Intel also incorporates a lower limit to ensure that compliance of the WLAN card is maintained. The minimum limits are set by factory processes. 7.2.2 Channel configuration – scan This section will be included in future revisions. 7.2.3 Output power restrictions for main geographies Table 7–1 Output power restrictions, main geographies Output Power (dBm) 2.4 GHz 5.15 – 5.25 GHz 5.25 – 5.35 GHz 5.47 – 5.65 GHz 5.65 – 5.725 GHz 5.725 – 5.85 GHz Unit EU Countries EIRP 20 23 23 233 233 14 SRD dBm > EU Countries Cond.1 17 18 18 18 18 9 SRD dBm 1000 250 250 250 250 1000 mW > United States Cond. 30 24 24 24 24 30 dBm Canada2 Cond. 1000 200 EIRP 250 250 250 1000 mW Canada2 Cond. 30 23 EIRP 24 24 24 30 dBm India 30 23 EIRP 23 EIRP N/A N/A 23 EIRP dBm 18 18 24 24 27 dBm Country/Geo United States2 Cond. China Cond. Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 42 Intel Confidential April 2017 Document Number: 567240–1.0 Regulatory Output Power (dBm) 2.4 GHz 5.15 – 5.25 GHz 5.25 – 5.35 GHz 5.47 – 5.65 GHz 5.65 – 5.725 GHz 5.725 – 5.85 GHz Unit 20 23 23 30 30 33 dBm Worst Case Cond. mW2 100 50 200 250 250 100 mW Worst Case Cond. dBm1 17 18 18 18 18 18 dBm Country/Geo China EIRP NOTES: Reference antenna gain: Max. Antenna Gain 3 dBi for 2.4 GHz and 5 dBi for 5 GHz 1. Assuming Max. Antenna Gain 3 dBi for 2.4 GHz and 5 dBi for 5 GHz 2. Allowance of up to a 6 dBi antenna allowed, if antenna is > 6 dBi output power must be reduced by 1 dB per dBi of antenna gain. 3. As DFS Slave Device (30 dBm for Master). 7.3 Regulatory and safety certification The following regulatory and safety information is subject to change. Table 7–2 USA Wi-Fi safety and regulatory USA Requirements Criteria EMI FCC Part 15, Subpart B, Class B (CISPR 22 limits at 10 m) RF FCC Part 15, Subpart C (Sections 15.205, 15.207, 15.209, and 15.247) FCC Part 15, Subpart E (Section 15.407) Safety Table 7–3 Europe UL 60950–1 Wi-Fi safety and regulatory Europe Requirements Criteria EMC EN301489–1, EN 301489–17 RF EN300 328, EN300 440 and EN301–893 as DFS slave terminal Safety EN60950–1 via CB Report (IEC60950–1) R&TTE Health Requirement referring to the EN 50566–2013 and 62209–2:2010 Table 7–4 Japan Wi-Fi safety and regulatory Japan Requirements Criteria EMI VCCI Class B RF STD T66, STD T71, ARIB W52, W53, W56 Safety EN60950–1 via CB Report (IEC60950–1) R&TTE Health Requirement referring to the EN 50566–2013 and 62209–2:2010 April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 43 Regulatory Table 7–5 Wi-Fi safety and regulatory Australia/New Zealand Australia/ New Zealand Table 7–6 Criteria EMC EU test reports RF Radio communications (EMR) Standard 2003; EU test reports + Delta AS–NZ4268 Safety CB Cert. and Report (IEC60950–1) Wi-Fi safety and regulatory other geographies Other Geographies Note: Requirements Requirements Criteria Priority 2 Countries To be covered in MWG Regulatory WW Country Coverage Priority 3 Countries To be covered in MWG Regulatory WW Country Coverage Regulatory pre-scans and certification are tested using a combo Bluetooth/Wi-Fi reference antenna. Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 44 Intel Confidential April 2017 Document Number: 567240–1.0 Dynamic Regulatory Solution Dynamic Regulatory Solution 8.1 Overview Beginning with the Intel® Dual Band Wireless 7265 module (Stone Peak 2/D), Intel® introduces a new Dynamic Regulatory Solution (DRS) which offers worldwide regulatory compliance on one hardware SKU, while offering optimizations to various country regulations based on geo–location discovery. These Wi-Fi optimizations bring the PC market up to capabilities offered in other segments, and include the following benefits: More robust regulatory compliance Consolidation to a single worldwide regulatory SKU Country–specific channel optimizations Minimized OEM effort on enablement, production, and inventory management Ability to meet changing regulations and field support with software updates Simpler worldwide procurement and distribution for enterprise customers The new dynamic solution provides a significant improvement in compliance reliability by ensuring the compliance always aligns to the adapter’s location. It also provides the ability to react more quickly to changing regulations, both in new product shipments as well as field upgrades. Changing regulations can be applied precisely to the relevant country or countries without impacting optimizations to any other country. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 45 Platform Design Guidelines Platform Design Guidelines This section includes important platform design and implementation aspects that the OEM should take into consideration when implementing a platform that would accommodate this product. Jefferson Peak is an integrated connectivity RF companion module, and there has special platform design guidelines are different from standard M.2 connectivity design features. Besides having new interface requirements, integrated connectivity allows designing the platform so as to support both integrated and discrete connectivity M.2 modules using a single platform design. This allows the OEM to have one motherboard design accommodating either a Companion RF module or a discrete M.2 card which can be “swappable” on the same M.2 socket. This section focuses on the dual CNVi/Discrete design, and therefore will include guidelines applicable to the Jefferson peak M.2 card as well as to other discrete M.2 cards. 9.1 Socket 1 key options for 2230 cards Socket 1 has two options: Key E and Key A. Each key with different supported list of I/Fs as defined in the M.2 specification. In general the different keys should be used in the following cases: Key E: When UART/I2S for BT is required. Key A: When WiGig with display port is required – N/A for 2017 products Hybrid Key E: When CNVi should be supported and when swappable CNVi/discrete should be supported In order to support the Jefferson Peak, or any other CNVi RF companion module the third option shall be used on the design. The Hybrid Key E can be designed in a few different variants allowing some level of flexibility including: • Supporting integrated connectivity (CNVi) only • Supporting swappable integrated/discrete connectivity (CNVi) 9.1.1 Socket 1 Hybrid Key E scheme The high level block diagram in Figure 9–1 shows the platform-level view of CNVi, including all related system components. Note that the connectivity block represents a few alternative options: Companion RF, Discrete, and Wi-Fi/BT/WiGig Combo, all of which can be used in the design but are mutually exclusive (only one can exist at a specific time).= Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 46 Intel Confidential April 2017 Document Number: 567240–1.0 Platform Design Guidelines Figure 9–1 Platform connections to CNVi – Hybrid Key E scheme CNVi related SW components: • WiFi, BT, WiGiG drivers • BIOS Connectivity Platform VRs 3.3v WPR Aiding I2C WWAN Modem WiFi/BT UART UART UART BRI 32KHz clock clkreq0 RF_RESET_B REFCLK0 SOC XTAL WiFi RF companion Discrete connectivity WiFi/BT/WiGiG Combo RGI CNVi related straps • • • CNVio WiGiG CLINK RFEM PCIe USB UART I2S 9.1.2 Connectorized Hybrid Key E (2230) pin-out The M.2 socket with the Hybrid Key E scheme is intended to be used with a proprietary pinout. This scheme is called “Hybrid Key E” due to the mechanical similarity to a Key E connector and the ability to support both Companion RF and discrete modules. When designing a motherboard with this scheme, one can have the same M.2 socket supporting three (3) different connectivity cards: (1) CNVi Companion RF module (CRF) (2) Standard M.2 discrete module (Discrete), and (3) WiGiG/Wi-Fi combo module (Combo) – N/A for 2017 products The ability to swap between these three cards on the same M.2 socket while using the same motherboard design is an important feature desired by PC platform OEMs. When designing the motherboard M.2 socket and routing according the Hybrid Key E scheme, and subject to certain assumptions that will be defined later, the following basic properties are guaranteed: • • Inserting any one of the three optional cards (Namely CRF, Discrete and Combo) to the M.2 socket will be safe (meaning no damage to the motherboard or card will occur). All 3 options can be used and will function as desired, subject to the following 1. For CNVi: No restrictions apply April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 47 Platform Design Guidelines 2. For Discrete: The most commonly used interfaces will work. Some interfaces will not be available and therefore some operation modes will not function. A list of restrictions on modes and interfaces can be found in Table 9–1. The pinout for the Hybrid Key E socket on the motherboard is shown in Figure 9–2. The inner columns show the Companion RF proprietary signals at their assigned pins. The Companion RF signals, listed with the prefix “/,” signify that they are electrically MUX’d inside the PCH/SoC and are shared. Due to this internal SoC sharing, these signals do not require any jumpers to select between the two functions. Note that there are six (6) such signals. Figure 9–2 2230 Hybrid Key E socket pinout (names refer to platform socket side) 9.1.3 Special considerations for the Hybrid Key E scheme The Hybrid Key E scheme relies on assigning multiple functions to M.2 connector pins and to PCH pins. This causes a significant reduction of the amount of signals that needs to be routed between the SoC and the M.2 Module at the expense of additional dependency between modes, and the loss of some functionality. The different dependencies between multiple functions pins and M.2 card functionality is described in the following section. Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 48 Intel Confidential April 2017 Document Number: 567240–1.0 Platform Design Guidelines Shared M.2 socket pins The following M.2 pins are shared between different functions: V3P3A, GND This is the M.2 card power supply (3.3V) and Ground pins, respectively. Both have multiple pins on the connector. These pins have the same purpose in either discrete or CNVi implementations, and therefore are not affected by the Hybrid Key E scheme. PCIe-1/CNVio These are six pins that are assigned to the PCIe-1 bus in the M.2 standard pinout. This bus has three differential pairs, two for the PCIe data lanes (one per direction) and one for the PCIe clock. In the Hybrid Key E scheme, these signals are used for the CNVio interface from Pulsar to the companion RF chip. Due to this sharing, the Hybrid Key E scheme does not support PCIe-1. SDIO/CNVio These are eight pins that are assigned to the SDIO bus in the M.2 standard pinout. This bus has eight signals, four bi-directional for the SDIO data, one bi-directional command signal, one clock (SoC to M.2) and two control (Reset SoC to M.2, Wake M.2 to SoC). In the Hybrid Key E scheme these signals are used for CNVio interface the RF companion chip to Pulsar (siz for CNVio and two for ground). Due to this sharing, the Hybrid Key E scheme does not support SDIO. PCM/ClockReq and Reset The standard M.2 defines four pins for a dedicated PCM audio serial bus. In the Hybrid Key E scheme, two of these signals are used for CNVi Clock (from RF companion to SoC) and Reset (For SoC to RF companion). Since the PCM serial bus is connected to PCH GPIO pins, and the CNVi clock request and reset pins are also connected to PCH GPIO pins, it is possible to have support for both PCM bus and CNVi signals by changing the PCH GPIO muxing function select. Due to this sharing, the Hybrid Key E scheme can still support PCM (for discrete connectivity with PCM support). UART (BT) / BRI and RGI The standard M.2 defines four pins for a dedicated UART serial bus for Bluetooth. In the Hybrid Key E scheme, all these signals are used for CNVi BRI (Bluetooth radio interface) and RGI (radio generic interface), each comprised of two signals (one per direction). Since the UART serial bus is connected to PCH GPIO pins, and the CNVi BRI and RGI are also connected to PCH GPIO pins, it is possible to have support for both the UART bus and CNVi signals by changing the PCH GPIO muxing function. Due to this sharing, the Hybrid Key E scheme can still support BT UART (for discrete connectivity with BTUART support). SUSCLK/P_32K These signals are both functionally similar. In the M.2 standard, this pin is optionally connected to a 32kHz RTC clock. In the Hybrid Key E scheme for CNVi, it should be connected to a 32kHz clock, which is not optional, and must be driven by a valid 32kHz clock any time the RF companion module is powered on. The 32kHz clock can come from a PCH pin or from a different source on the platform, depending on the platform used. For CNL, this signal comes from the PCH. In Gemini Lake it is connected to the SoC. GND/LNA_EN This signal is used for different purposes in CNVi and discrete, but in both cases should be connected to ground; therefore, it does not affect functionality. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 49 Platform Design Guidelines NFC I/F, and A4WP+Ref clock In the Hybrid Key E scheme, only one of these four signals is used. This REFCLK0 signal connects the reference clock (single ended, 1V p-p, 38.4MHz) from the RF companion to the SoC. The remaining three signals are not used. Non-shared M.2 socket pins Some pins on the M.2 connector are not shared, meaning they are not used for any CNVi function. The functions of these pins can still be impacted by the Hybrid key E scheme as will be described here. PEWake1#, CLKREQ1#, PERST1# These are three control signals used by the PCIe-1 bus in standard M.2 cards. Although these signals are not shared with any other function, they have no usage in a Hybrid Key E scheme design. This is because the PCIe-1 bus by itself is not usable. (See “PCIe-1/CNVio,” above.) PCIe-0 Bus This consists of six signals (three differential pairs) used for PCIe data to and from the SoC, and a single pair used for the PCIe bus clock. In a CNVi RF companion, these signals are left unused. In a discrete module, these signals are being used as the Wi-Fi bus interface. W_DISABLE1#, W_DISABLE2# These are used for Wi-Fi and BT RF-KILL control, respectively. (Asserting these signals shuts off the RF transmission or the relevant core.) The functions of these signals are the same for Hybrid Key E, and therefore they are not affected by this scheme. PEWake0#, CLKREQ0#, PERST0# These are three control signals used by the PCIe-0 bus in standard M.2 cards. They should be routed to SoC pins that are assigned to GPIOs in Discrete or Combo modes. Coex UART interface This interface consists of three signals (two UART bus signals and one GPIO). They are used for Wi-Fi/BT-LTE coexistence signaling in the M.2 standard definition. Since these pins are left unused in the RF companion, they can still be used with a discrete M.2 card even when designing with the Hybrid Key E scheme. In platforms that are designed to support a WWAN modem and Hybrid Key E, there should be three pins connected to each signal, to allow the modem to connect to the M.2 pin (in the discrete connectivity case) or to the PCH (in the CNVi case). CLINK interface This interface consists of three signals (clock, data and reset). This bus in an Intel-proprietary bus. Since these pins are left unused in the RF companion, they can still be used with a discrete M.2 card, even when designing with the Hybrid Key E scheme. LED1, LED2 These are optional pins that are assigned to drive LEDs on the platform in the standard M.2 cards. They are used for the same function when using CNVi, and therefore are not affected by the Hybrid Key E scheme. USB bus The standard M.2 defines two pins for a differential USB bus. This bus has no usage in the RF companion. When using a standard M.2 discrete card, the pins will have the standard functionality and are not affected by the Hybrid Key E scheme. The different connectivity interfaces as used by a discrete connectivity (Standard M.2, Intel connectivity, or TPV) and CNVi RF companion card are summarized in Table 9–1. The table also points to the different restrictions posed by the use of a Hybrid Key E socket design on the motherboard. Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 50 Intel Confidential April 2017 Document Number: 567240–1.0 Platform Design Guidelines Table 9–1 Hybrid Key E interface mapping for different connectivity cards M.2 Interface CNVi Discrete PCIe-1 M.2 pins are not connected to the CRF. Wi-Fi uses internal IOSF to interface the host. Used for Wi-Fi host interface PCIe-2 Not functional Not functional Pins are connected to CRF and Pulsar CNVio and can’t be used as PCIe. Pins are connected to Pulsar CNVio and can’t be used as PCIe. Not functional Not functional Pins are connected to CRF and Pulsar CNVio and can’t be used as SDIO. Pins are connected to Pulsar CNVio and can’t be used as SDIO. Wi-Fi CLINK M.2 pins are not connected to the CRF. Wi-Fi uses internal CLINK to interface the ME. Used for Wi-Fi CSME interface Wi-Fi RF-KILL Used (optional) Used (optional) BT USB M.2 pins are not connected to the CRF. BT uses internal U2U to interface the host. Used for BT USB interface BT UART M.2 pins are not connected to the CRF. BT uses internal UART to interface the host. Used for BT UART interface BT I2S (Audio) M.2 pins are not connected to the CRF. BT uses internal I2S to interface the host. Used for BT I2S interface BT wake M.2 pin is not connected to the CRF. BT uses internal vGPIO. Used for BT wake signal BT RF-KILL Used (optional) Used (optional) NFC Not functional Not functional Pins are connected to A4WP bus and to Refclock (38.4M system clock) and can’t be used for NFC. Pins are connected to A4WP bus and to Refclock (38.4M system clock) and can’t be used for NFC. I2C bus to A4WP Used for A4WP support to connect to platform WPR module. Used for A4WP support to connect to platform WPR module. 3.3V Power supply pins Used per M.2 standard Used per M.2 standard GND Used per M.2 standard Used per M.2 standard Wi-Fi SDIO 9.1.4 Soldered-down (1216) pin-out The RF Companion SD-1216 module has the same mechanical outline as the standard M.2 connectivity type 1216-S3. The standard M.2 land pattern is modified to accommodate the proprietary the RF companion module signals. Instead, it has an additional set of solder pads which don’t overlap with the standard solder pads. This allows having a single motherboard design that can accommodate April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 51 Platform Design Guidelines either a standard M.2 1216 card or an RF companion 1216 card. However, unlike in the connectorized case, swapping cards requires removing a soldered-down module, and so can’t be done with a simple socket card exchange. Additionally, the assembly tooling and BOM should change between a discrete and CNVi motherboard assembly. The special pad-out required for supporting CNVi and discrete is shown in Figure 9–3 and Figure 9–4. (TBD: Add a diagram/table for connection diagram to show which pins can be shortened to enable easier layout). Figure 9–3 SD-1216 module pad-out for supporting CNVi and Discrete 1216 modules Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 52 Intel Confidential April 2017 Document Number: 567240–1.0 Platform Design Guidelines Figure 9–4 SD-1216 module pad-out for supporting CNVi and Discrete 1216 modules 9.1.5 Breakout example for JfP soldered-down module The soldered-down JfP module has a special pad shape, which combines the standard M.2 pad ring on the outside with the new inner ring of the CNVi pads. It is recommended that the OEM consider all signal properties when designing the motherboard for dual discrete/CNVi design supporting Jefferson Peak 1216. An example for the breakout layout for a type-3 board (with no micro-via) is shown in Figure 9–5. Note that in order to keep the picture clear, this example shows only two signal layers (top layer and third layer) while the other layers are not shown. Also there is an assumption that the second layer shall be ground. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 53 Platform Design Guidelines G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND Board layout example showing breakout from JfP 1216 pads (design for CNVi only) G ND Figure 9–5 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 G ND G1 G4 G ND 76 G ND 75 G ND 74 G ND Powe r 3.3V 3.3V 73 3.3V 72 3.3V A7 10 A8 13 A11 14 A12 15 A13 16 A14 17 A15 18 A16 19 A17 20 A18 21 A19 22 A20 23 A21 24 A22 25 A23 26 A24 SUSCLK 27 A25 W_DISA BLE 1# 28 G ND G2 NC +3.3V NC +3.3V NC NC NC NC NC NC NC REFCLK0 CLKREQ0 RF_RESET_B NC RG I_RSP NC RG I_DT NC BRI_RSP W T_CLK+ BRI_DT W T_CLK- W GR_D1- W T_D0+ W GR_D1+ W T_D0- W GR_D0- W T_D1+ W GR_D0+ W T_D1- W GR_CLK- C_P32K G ND W GR_CLK+ NC G ND A26 A27 A28 NC A29 A30 A48 66 A47 65 LED1# 64 LED2# W iFi LE D A44 63 W_DISA BLE 2# 62 G ND BT RF_KILL A43 61 A42 60 A41 59 A40 58 A39 57 A38 56 A37 55 A36 54 A35 53 A34 52 A33 51 A32 50 A45 G ND NC 68 G ND 67 A46 NC NC A49 A31 49 BT LE D CLKREQ RF_RE SE T_B CNVi o RX A10 G ND BRI A9 12 A50 G ND RGI W iFi RF_KILL 69 11 CNVi o TX 32Khz clock Powe r 71 G ND 70 G3 G ND G ND G ND G ND G ND 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 54 Intel Confidential April 2017 Document Number: 567240–1.0 Platform Design Guidelines G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND G ND Board layout example showing breakout from JfP 1216 pads (dual design for CNVi and discrete) G ND Figure 9–6 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 G ND 74 G ND 3.3V 73 Coex sig na ls Powe r 3.3V 3.3V 72 3.3V 71 G ND 70 U SB _D+ 69 U SB _D- A50 68 G ND A49 67 A48 66 A47 65 LED1# A46 64 LED2# A45 63 W_DISA BLE 2# A44 62 G ND A43 61 PCM_CLK A42 60 PCM_IN A41 59 PCM_OUT A40 58 PCM_SYNC A39 57 U ART_CTS A38 56 U ART_TXD A37 55 U ART_RXD A36 54 U ART_RTS A35 53 U ART_W AKE# A34 52 A33 51 A32 50 A7 A8 11 A9 COEX_RXD 12 A10 COEX3 13 A11 14 A12 15 A13 16 A14 17 A15 18 A16 19 A17 20 A18 21 A19 22 A20 23 A21 24 A22 25 A23 CNVi o TX 10 COEX_TXD 26 A24 32Khz clock SUSCLK 27 A25 W iFi RF_KILL W_DISA BLE 1# 28 G ND G2 G ND G ND NC +3.3V NC +3.3V NC NC NC NC NC NC NC REFCLK0 NC CLKREQ0 G ND RF_RESET_B NC RG I_RSP NC RG I_DT NC BRI_RSP W T_CLK+ BRI_DT W T_CLK- W GR_D1- W T_D0+ W GR_D1+ W T_D0- W GR_D0- W T_D1+ W GR_D0+ W T_D1- W GR_CLK- C_P32K G ND W GR_CLK+ NC G ND A26 NC NC A27 A28 NC A29 A30 A31 49 G3 Powe r BT US B W iFi LE D BT LE D BT RF_KILL RE FCLK 38.4M hz CLKREQ RF_RE SE T_B BRI 75 RGI G ND GPIO CNVi o RX G ND 76 UA RT G4 I2S G1 G ND G ND W iFi PCI e 9.1.6 CLINK _RST CLINK _DA T CLINK _CLK PET0+ PET0- G ND G ND PER0+ PER0- G ND REFCLK0+ REFCLK0- G ND RERST# CLKREQ# PEW AKW# 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 CLIN K Signal connection pitfalls The OEM should make sure to follow the M.2 definitions of signal names and directions (I/O TX/Rx etc.) and avoid confusion between platform side and device side. Note that some lines are bidirectional, such as PCIe CLKREQ, PEWAKE. 9.1.7 Pullups and pulldowns The OEM should apply pullups and pulldowns in the platform side according to Table 9–2. Table 9–2 Socket 1 pullups and pulldowns I/F Signals PU/PD Guideline Rationale BRI/RGI BRI_DT / RTS None Intel SoC with CNVi support have internal PU/PD as needed. RGI_RSP / CTS PU Intel SoC with CNVi support have internal PU/PD as needed. BT UART April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 55 Platform Design Guidelines I/F Signals PU/PD Guideline Rationale BRI_RSP / Rx PU Intel SoC with CNVi support have internal PU/PD as needed. RGI_DT / Tx BT UART WAKE# PU Open drain, required by M.2 PU Required by Intel platform design guidelines PEWAKE# PU Open drain, required by M.2 CLKREQ# PU Open drain, required by M.2 PERST# PD Required by Intel platform design guidelines Other PCIe signals None PCIe spec RefCLK PD W_Disable# PCIe 38.4 Ref clock Intel SoC with CNVi support have internal PU/PD as needed. The OEM must avoid using PU/PD when not needed or when required not to be used. If this rule is not followed, it will result in a back-bias condition, where the IO is getting voltage before the device side is ready for it. 9.1.8 IO connection scenarios and best practices The motherboard designer should address the following requirements for the sake of avoiding failsafe problems, reducing unneeded leakage, and for following best-practice design rules: Level-shifter back-bias prevention – Level shifter shall not set value in A side when not getting voltage in B side. – Rationale: Prevent back-bias and wrong logic conditions. Level shifters shall be back-bias protected. 9.1.9 Rationale: The level shifter is often supplied with a different supply than the IO connected to it. During ramp up/down states there might be a back-bias scenario. I/F specific guidelines CNVio signals The CNVio signals connect the RF companion module and the SoC. They are used as the main data bus for Wi-Fi to transfer data between the Pulsar and the RF companion chip. The CNVio signals are PHYsically similar to the MiPi DPHY standard, but have a different (and Intel-proprietary) protocol. Since the PHYsical layer of the CNVio is similar to a standard, the user should follow the MiPi DPHY routing signal requirements. These are well documented in the MiPi DPHY standard specification. (See Chapter 7 of the MiPi DPHY standard: “Interconnect and Lane Configuration.”) The CNVio bus is source synchronous, and runs at a clock rate of 1280Mhz. Each lane has data carried over a differential pair, and each direction may have multiple lanes and a single clock, driven by the source. Routing The routes of the two traces of each lane must match as much as possible. Moreover, since the CNVio uses one clock signal for multiple lanes in each direction, there should also be good delay matching Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 56 Intel Confidential April 2017 Document Number: 567240–1.0 Platform Design Guidelines between the two data lanes and the clock. There are no special delay-matching requirements between lanes in opposite directions. Table 9–3 CNVio recommended parameters Parameter Value Comment Differential pair length matching: 0.02UI This parameters may effect EMI and RFI Characteristic impedance 100 ohm differential 50 ohm to ground for each trace Maximum length 10 inch 9 inch from M.2 connector pins to SoC pins Maximum resistance 5 ohm 50 ohm to ground for each trace Shielding Berried microstrip (Stripline) Recommended for minimizing EMI/RFI Delay matching between pairs of the same direction Better than 80 mil Including the 2 lanes and the clock in every direction Vias Minimize usage Recommended to avoid Via connections as much as possible and follow differential BER 1E-12 Standard PHY bit error rate for a CNVio lane For 1280M: <80 mil RGI and BRI signals These are GPIO signals (1.8V) running between the SoC and the RF companion module. The BRI and RGI signals share the same traces as UART signals (for discrete). Since the UART baud rate is expected to be lower than the BRI/RGI toggle rate, it can be assumed that the BRI/RGI sets the requirements for this bus. BRI and RGI are two bi-directional busses. No special control impedance is needed. The BRI and RGI packets are protected by error-correction coding and with standard routing and signal integrity practices applied, no errors are expected to be noticed on the busses. 38.4M reference clock signal Ref Clock is a 38.4M clock signal which is generated by the RF companion module and sent to the SoC. This clock can be used as the SoC main clock (in clock sharing configuration) or as the Pulsar clock (in non-clock sharing configuration). When using the latter option, the SoC should have another clock for its operation, but Pulsar (within the SoC) will always get the 38.4M clock coming from the Companion RF module. The clock signal is a 1V nominal, 10Kohm typical resistive load with 35pF load capacitance. It is recommended to route the clock with special care while maintaining clock routing practices, preferably as a microstrip to minimize EMI/RFI and susceptibility to noise. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 57 Platform Design Guidelines Wi-Fi/BT/LTE coexistence signals In order to allow a Hybrid Key E scheme supporting both connectivity and a cellular modem, there is a need to connect the modem coexistence bus in a configuration that will allow the modem to connect to the connectivity coexistence control logic. In Intel connectivity modules, this logic may reside in the M.2 module or in the SoC, depending on whether the CNVi or discrete solutions are used: For CNVi, the logic that is connected to the coexistence bus resides in Pulsar, which is part of the SoC. For discrete M.2 cards, this logic resides in the module. • • As a result, when a motherboard design contains a modem, and it is desired that it be able to support CNVi and discrete on the same M.2 socket, there is a need to have a 3-way connection of the board, as shown in Figure 9–7. In this diagram, the red lines represent lines that are unused in each connection scenario. One can simplify the routing by adding a jumper resistor to select between the two configurations; however, this will result in losing the option to swap between CNVi and Discrete on the board. Any such swapping will then require a board hardware change for changing the jumper resistor position. Note that when doing this 3-way connection between SoC, M.2 and the modem, there will always be an unused signal that is not optimally terminated for that connection. This signal is shown in red in the connection diagram. The effect of this signal is similar to a stub that adds undesired impedance change to the trace. The effect of this stub on the UART bus depends on several system parameters: distance between the different UART pins, UART bus speed, and electrical characteristics of the UART drivers and receivers (referenced to the signal pins). This effect must be considered and analyzed through design practices or simulations to ensure that signal integrity is not compromised. For this analysis, the UART baud rate shall be assumed to not be higher than 4Mbaud. Figure 9–7 Coexistence UART for connectivity/modem 3-way configuration SOC M.2- CNVi SOC Pulsar Pulsar Coex UART Coex UART M.2- discrete Coex UART COEX3 Coex UART COEX3 Cellular Modem 9.1.10 Coex UART COEX3 Cellular Modem Connectivity module power control The connectivity module power supply pins shall be connected directly to the rail DSW. To ensure proper operation of the integrated connectivity module, the use of a power switch to control the M.2 module power shall be avoided. The Jefferson Peak module is not compatible with the SLP_WLAN control signal. Note that the Jefferson Peak module was designed with low-leakage power, and therefore does not require any external power control to be used during normal operation. Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) 58 Intel Confidential April 2017 Document Number: 567240–1.0 Platform Design Guidelines 9.1.11 Power supply de-coupling It is required to have decoupling caps on the power feeds in each end of the connector. 10uF+0.1uF+0.01uF at one end of socket in support of 3.3 V pins 2 and 4 (in 2230 modules) or pins 4 and 5 (in 1216 modules). 10uF+0.1uF+0.01uF at the other end of the socket in support of 3.3 V pins 70 and 72 (in 2230 modules) or pins 72 and 73 (in 1216 modules). 9.1.12 Wi-Fi wireless disable and HW RF-KILL W_DISABLE1# (pin 56 in M.2 2230 pinout, pin 28 in M.2 1216 SD pinout) serves as HW RF-KILL for the Wi-Fi radio. The pin is recommended to be left unconnected if the HW RF-KILL signal is not required. Asserting W_DISABLE#_1 signal will result in a complete shutdown of the Wi-Fi part. The result from the user perspective is similar to removing the Bluetooth device from the laptop. Note that HW RFKILL is supported on M.2 2230 modules only. 9.1.13 M.2 Bluetooth HW RF-KILL W_DISABLE2# (pin 54 in M.2 2230 pinout, pin 63 in M.2 1216 SD pinout) serves as HW RF-KILL for the Bluetooth radio. Asserting W_DISABLE#_2 signal will result in a complete shutdown of the Bluetooth part. The result from the user perspective is similar to removing the Bluetooth device from the platform. 9.1.14 BIOS The CNVi modules (including Jefferson Peak) require specific BIOS support. A full description of BIOS support needed for the Cannon Lake and Gemini Lake platforms can be found in the Connectivity BIOS Guide documents. April 2017 Document Number: 567240–1.0 Intel® Wireless-AC 9560 (Jefferson Peak) External Product Specification (EPS) Intel Confidential 59 警語 經型式認證合格之低功率射頻電機，非經許可，公司、商號或使用者均不得擅自變 更頻率、加大功率或變更原設計之特性及功能。 (即低功率電波輻射性電機管理辦法第十二條) 低功率射頻電機之使用不得影響飛航安全及干擾合法通信；經發現有干擾現象時， 應立即停用，並改善至無干擾時方得繼續使用。 前項合法通信，指依電信法規定作業之無線電通信。低功率射頻電機須忍受合法通 信或工業、科學及醫療用電波輻射性電機設備之干擾。 (即低功率電波輻射性電機管理辦法第十四條) 本模組於取得認證後將依規定於模組本體標示審驗合格標籤，並要求最終產品平台 廠商(OEM Integrator)於最終產品平台(End Product)上標示” 本產品內含射頻模 組，其 NCC 型式認證號碼為: CCXXxxYYyyyZzW REGULATORY INFORMATION USA - Federal Communications Commission (FCC) This wireless adapter is restricted to indoor use due to its operation in the 5.15 to 5.25 and 5.470 to 5.75GHz frequency ranges. No configuration controls are provided for Intel® wireless adapters allowing any change in the frequency of operations outside the FCC grant of authorization for U.S. operation according to Part 15.407 of the FCC rules. Intel® wireless adapters are intended for OEM integrators only. Intel® wireless adapters cannot be co-located with any other transmitter unless approved by the FCC. This wireless adapter complies with Part 15 of the FCC Rules. Operation of the device is subject to the following two conditions: This device may not cause harmful interference. This device must accept any interference that may cause undesired operation. NOTE: The radiated output power of the adapter is far below the FCC radio frequency exposure limits. Nevertheless, the adapter should be used in such a manner that the potential for human contact during normal operation is minimized. To avoid the possibility of exceeding the FCC radio frequency exposure limits, you should keep a distance of at least 20cm between you (or any other person in the vicinity), or the minimum separation distance as specified by the FCC grant conditions, and the antenna that is built into the computer. Details of the authorized configurations can be found at http://www.fcc.gov/oet/ea/ by entering the FCC ID number on the device. Class B Device Interference Statement This wireless adapter has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This wireless adapter generates, uses, and can radiate radio frequency energy. If the wireless adapter is not installed and used in accordance with the instructions, the wireless adapter may cause harmful interference to radio communications. There is no guarantee, however, that such interference will not occur in a particular installation. If this wireless adapter does cause harmful interference to radio or television reception (which can be determined by turning the equipment off and on), the user is encouraged to try to correct the interference by taking one or more of the following measures: Reorient or relocate the receiving antenna of the equipment experiencing the interference. Increase the distance between the wireless adapter and the equipment experiencing the interference. Connect the computer with the wireless adapter to an outlet on a circuit different from that to which the equipment experiencing the interference is connected. Consult the dealer or an experienced radio/TV technician for help. NOTE: The adapter must be installed and used in strict accordance with the manufacturer's instructions as described in the user documentation that comes with the product. Any other installation or use will violate FCC Part 15 regulations. Canada – Industry Canada (IC) This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Cet appareil se conforme aux normes Canada d'Industrie de RSS permis-exempt. L'utilisation est assujetti aux deux conditions suivantes: (1) cet appareil ne peut pas causer d'interférences, et (2) cet appareil doit accepter des interférences , y compris des interférences qui peuvent causer desopérations non désirées de l'appareil. Caution: When using IEEE 802.11a wireless LAN, this product is restricted to indoor use due to its operation in the 5.15- to 5.25-GHz frequency range. Industry Canada requires this product to be used indoors for the frequency range of 5.15GHz to 5.25GHz to reduce the potential for harmful interference to co-channel mobile satellite systems. High power radar is allocated as the primary user of the 5.25- to 5.35-GHz and 5.65 to 5.85-GHz bands. These radar stations can cause interference with and/or damage to this device. The maximum allowed antenna gain for use with this device is 6dBi in order to comply with the E.I.R.P limit for the 5.25- to 5.35 and 5.725 to 5.85GHz frequency range in point-to-point operation. To comply with RF exposure requirements all antennas should be located at a minimum distance of 20cm, or the minimum separation distance allowed by the module approval, from the body of all persons. Attention: l'utilisation d'un réseau sans fil IEEE802.11a est restreinte à une utilisation en intérieur à cause du fonctionnement dans la bande de fréquence 5.15-5.25 GHz. Industry Canada requiert que ce produit soit utilisé à l'intérieur des bâtiments pour la bande de fréquence 5.15-5.25 GHz afin de réduire les possibilités d'interférences nuisibles aux canaux co-existants des systèmes de transmission satellites. Les radars de puissances ont fait l'objet d'une allocation primaire de fréquences dans les bandes 5.25-5.35 GHz et 5.65-5.85 GHz. Ces stations radar peuvent créer des interférences avec ce produit et/ou lui être nuisible. Le gain d'antenne maximum permissible pour une utilisation avec ce produit est de 6 dBi afin d'être conforme aux limites de puissance isotropique rayonnée équivalente (P.I.R.E.) applicable dans les bandes 5.25-5.35 GHz et 5.725-5.85 GHz en fonctionnement point-àpoint. Pour se conformer aux conditions d'exposition de RF toutes les antennes devraient être localisées à une distance minimum de 20 cm, ou la distance de séparation minimum permise par l'approbation du module, du corps de toutes les personnes. Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. Selon les règlements de Canada d'Industrie, cet émetteur de radio peut seulement fonctionner en utilisant une antenne du type et de gain maximum (ou moindre) que le gain approuvé pour l'émetteur par Canada d'Industrie. Pour réduire lesinterférences radio potentielles avec les autres utilisateurs, le type d'antenne et son gain devraient être choisis de façon à ce que la puissance isotrope rayonnée équivalente(P.I.R.E.) ne soit pas supérieure à celle qui est nécessaire pour une communication réussie. Safety Approval Considerations This device has been safety approved as a component and is for use only in complete equipment where the acceptability of the combination is determined by the appropriate safety agencies. When installed, consideration must be given to the following: It must be installed into a compliant host device meeting the requirement of UL/EN/IEC 60950-1 2nd edition including the general provisions of enclosure design 1.6.2 and specifically paragraph 1.2.6.2 (Fire Enclosure). The device shall be supplied by a SELV source when installed in the end-use equipment. A heating test shall be considered in the end-use product for meeting the requirement of UL/EN/IEC 60950-1 2nd edition. Japan 5GHz 帯は室内でのみ使用のこと Korea 해당 무선설비는 전파혼신 가능성이 있으므로 인명안전과 관련된 서비스는 할 수 없음. 해당 무선 설비는 5150-5250MHz 대역에서 실내에서만 사용할 수 있음. Mexico La operación de este equipo está sujeta a las siguientes dos condiciones: (1) es posible que este equipo o dispositivo no cause interferencia perjudicial y (2) este equipo o dispositivo debe aceptar cualquier interferencia, incluyendo la que pueda causar su operación no deseada. Radio Approvals To determine whether you are allowed to use your wireless network device in a specific country, please check to see if the radio type number that is printed INFORMATION FOR OEMs and HOST INTEGRATORS The guidelines described within this document are provided to OEM integrators installing Intel® wireless adapters in notebook and tablet PC host platforms. Adherence to these requirements is necessary to meet the conditions of compliance with FCC rules, including RF exposure. When all antenna type and placement guidelines described herein are fulfilled the Intel® wireless adapters may be incorporated into notebook and tablet PC host platforms with no further restrictions. If any of the guidelines described herein are not satisfied it may be necessary for the OEM or integrator to perform additional testing and/or obtain additional approval. The OEM or integrator is responsible to determine the required host regulatory testing and/or obtaining the required host approvals for compliance. Intel® wireless adapters are intended for OEMs and host integrators only. The Intel® wireless adapter FCC Grant of Authorization describes any limited conditions of modular approval. The Intel® wireless adapters must be operated with an access point that has been approved for the country of operation. Changes or modification to Intel® wireless adapters by OEMs, integrators or other third parties is not permitted. Any changes or modification to Intel
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| Document ID | 3645255 |
| Application ID | 4zCe5TDGXJEXbNscioQRJg== |
| Document Description | (9560NGW) User Manual |
| Short Term Confidential | No |
| Permanent Confidential | No |
| Supercede | Yes |
| Document Type | User Manual |
| Display Format | Adobe Acrobat PDF - pdf |
| Filesize | 445.81kB (5572656 bits) |
| Date Submitted | 2017-11-20 00:00:00 |
| Date Available | 2017-11-20 00:00:00 |
| Creation Date | 2017-04-13 15:57:01 |
| Producing Software | 3-Heights(TM) PDF Security Shell 4.8.25.2 (http://www.pdf-tools.com) |
| Document Lastmod | 2017-10-17 17:37:17 |
| Document Title | Intel® Wireless-AC 9560 (Jefferson Peak) |
| Document Creator | Acrobat PDFMaker 17 for Word |
| Document Author: | Intel Corporation |
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf Linearized : No Author : Intel Corporation CC Version : \main\36 CTP Classification : CTP_IC CTP BU : INFORMATION TECHNOLOGY GRP CTP Time Stamp : 2017-04-13 22:56:23Z Company : Intel Corporation Create Date : 2017:04:13 15:57:01-07:00 Document Name : Intel® Dual Band Wireless-AC 9560 (Jefferson Peak) EPS Document Number : 567240 Keywords : Intel, Dual-Band Wireless-AC, 9560, Jefferson Peak, Wi-Fi, Next-Gen Wi-Fi, 802.11ac, 802.11n, wireless, Wi-Fi Direct, dual-band, multi-stream, 2 in 1, business, Intel Wi-Fi, EPS Modify Date : 2017:10:17 17:37:17+08:00 Source Modified : D:20170413225634 Titus GUID : acea57a2-a0df-4619-bbc9-cd620e8e806e Version : 1.0 Has XFA : No Language : EN-US Tagged PDF : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-20:48:00 Metadata Date : 2017:10:17 17:37:17+08:00 Creator Tool : Acrobat PDFMaker 17 for Word Document ID : uuid:6436ebfd-d4f7-4a78-93b1-0068e350b0f3 Instance ID : uuid:816e17f1-ff0e-423f-a03b-723757217e55 Format : application/pdf Title : Intel® Wireless-AC 9560 (Jefferson Peak) Description : External Product Specification (EPS) Creator : Intel Corporation Subject : Intel, Dual-Band Wireless-AC, 9560, Jefferson Peak, Wi-Fi, Next-Gen Wi-Fi, 802.11ac, 802.11n, wireless, Wi-Fi Direct, dual-band, multi-stream, 2 in 1, business, Intel Wi-Fi, EPS Producer : 3-Heights(TM) PDF Security Shell 4.8.25.2 (http://www.pdf-tools.com) PDF Version : 1.6 Document 0020 Name : Intel® Dual Band Wireless-AC 9560 (Jefferson Peak) EPS Document 0020number : 567240 Ctp Bu : INFORMATION TECHNOLOGY GRP Headline : External Product Specification (EPS) Page Layout : OneColumn Page Count : 64
