GCC 8 Release Series
Changes, New Features, and Fixes

This page is a "brief" summary of some of the huge number of improvements in GCC 8. You may also want to check out our Porting to GCC 8 page and the full GCC documentation.

Disclaimer: GCC 8 has not been released yet, so this document is a work-in-progress.

Caveats

• Support for the obsolete SDB/coff debug info format has been removed. The option -gcoff no longer does anything.
• The Cilk+ extensions to the C and C++ languages were removed from GCC.
• The MPX extensions to the C and C++ languages have been deprecated and will be removed in a future release.

General Improvements

• Inter-procedural optimization improvements:
  • Reworked run-time estimation metrics leading to more realistic guesses driving inliner and cloning heuristics.
  • The ipa-pure-const pass is extended to propagate the malloc attribute, and the corresponding warning option Wsuggest-attribute=malloc emits a diagnostic for a function, which can be annotated with malloc attribute.
• Profile driven optimization improvements:
  • New infrastructure for representing profiles (both statically guessed and profile feedback) which allows propagation of additional information about the reliability of the profile.
  • A number of improvements in the profile updating code solving problems found by new verification code.
  • Static detection of code which is not executed in a valid run of the program. This includes paths which trigger undefined behavior as well as calls to functions declared with the cold attribute. Newly the noreturn attribute does not imply all effects of cold to differentiate between exit (which is noreturn) and abort (which is in addition not executed in valid runs).
  • -freorder-blocks-and-partition, a pass splitting function bodies into hot and cold regions, is now enabled by default at -O2 and higher for x86 and x86-64.
• Link-time optimization improvements:
  • On ELF targets using DWARF debug information has been significantly improved in quality by properly preserving language-specific debug information. This allows for example the libstdc++ pretty-printers to work with LTO optimized executables.
• A new option -fcf-protection=[full|branch|return|none] is introduced to perform code instrumentation to increase program security by checking that target addresses of control-flow transfer instructions (such as indirect function call, function return, indirect jump) are valid. Currently the instrumentation is supported on x86 GNU/Linux targets only. See the user guide for further information about the option syntax and section "New Targets and Target Specific Improvements" for IA-32/x86-64 for more details.
• The polyhedral-based loop nest optimization pass -floop-nest-optimize has been overhauled. It's still considered experimental and may not result in any runtime improvements.
• Two new classical loop nest optimization passes have been added. -floop-unroll-and-jam performs outer loop unrolling and fusing of the inner loop copies. -floop-interchange exchanges loops in a loop nest to improve data locality. Both passes are enabled by default at -O3 and above.
• The new option -fstack-clash-protection causes the compiler to insert probes whenever stack space is allocated statically or dynamically to reliably detect stack overflows and thus mitigate the attack vector that relies on jumping over a stack guard page as provided by the operating system.

New Languages and Language specific improvements

Ada

BRIG (HSAIL)

In this release cycle, the focus for the BRIGFE was on stabilization and performance improvements. Also a couple of completely new features were added.

• Improved support for function and module scope group segment variables. PRM specs define function and module scope group segment variables as an experimental feature. However, PRM test suite uses them. Now group segment is handled by separate book keeping of module scope and function (kernel) offsets. Each function has a "frame" in the group segment offset to which is given as an argument, similar to traditional call stack frame handling.
• Reduce the number of type conversions due to the untyped HSAIL regs. Instead of always representing the HSAIL's untyped registers as unsigned int, the gccbrig now pre-analyzes the BRIG code and builds the register variables as a type used the most when storing or reading data to/from each register. This reduces the number of total casts which cannot be always optimized away.
• Support for BRIG_KIND_NONE directives.
• Made -O3 the default optimization level for BRIGFE.
• Fixed illegal addresses generated from address expressions which refer only to offset 0.
• Fixed a bug with reg+offset addressing on 32b segments. In 'large' mode, the offset is treated as 32bits unless it's in global, readonly or kernarg address space.
• Fixed a crash caused sometimes by calls with more than 4 args.
• Fixed a misexecution issue with kernels that have both unexpanded ID functions and calls to subfunctions.
• Treat HSAIL barrier builtins as setjmp/longjump style functions to avoid illegal optimizations.
• Ensure per WI copies of private variables are aligned correctly.
• libhsail-rt: Assume the host runtime allocates the work group memory.

C family

• New command-line options have been added for the C and C++ compilers:
  • -Wmultistatement-macros warns about unsafe macros expanding to multiple statements used as a body of a clause such as if, else, while, switch, or for.
• -fno-strict-overflow is now mapped to -fwrapv -fwrapv-pointer and signed integer overflow is now undefined by default at all optimization levels. Using -fsanitize=signed-integer-overflow is now the preferred way to audit code, -Wstrict-overflow is deprecated.

C++

Fortran

• The main version of libfortran has been changed to 5.
• Parameterized derived types, a major feature of Fortran 2003, have been implemented.
• The maximum rank for arrays has been increased to 15, conforming to the Fortran 2008 standard.
• Transformational intrinsics are now fully supported in initialization expressions.
• New flag -fc-prototypes to write C prototypes for BIND(C) procedures and variables.
• If -fmax-stack-var-size is honored if given together with -Ofast, -fstack-arrays is no longer set in that case.
• New options -fdefault-real-16 and -fdefault-real-10 to control the default kind of REAL variables.
• A warning is now issued if an array subscript inside a DO loop could lead to an out-of-bounds-access. The new option -Wdo-subscript, enabled by -Wextra, warns about this even if the compiler can not prove that the code will be executed.
• The Fortran front end now attempts to interchange loops if it is deemed profitable. So far, this is restricted to FORALL and DO CONCURRENT statements with multiple indices. This behavior be controlled with the new flag -ffrontend-loop-interchange, which is enabled with optimization by default. The -Wfrontend-loop-interchange option warns about such occurrences.
• When an actual argument contains too few elements for a dummy argument, an error is now issued. The -std=legacy option can be used to still compile such code.
• The RECL= argument to OPEN and INQUIRE statements now allows 64-bit integers, making records larger than 2GiB possible.
• The GFORTRAN_DEFAULT_RECL environment variable no longer has any effect. The record length for preconnected units is now larger than any practical limit, same as for sequential access units opened without an explicit RECL= specifier.
• Character variables longer than HUGE(0) elements are now possible on 64-bit targets. Note that this changes the procedure call ABI for all procedures with character arguments on 64-bit targets, as the type of the hidden character length argument has changed. The hidden character length argument is now of type INTEGER(C_SIZE_T).

Go

libgccjit

New Targets and Target Specific Improvements

AArch64

• The Armv8.4-A architecture is now supported. It can be used by specifying the -march=armv8.4-a option.
• The Dot Product instructions are now supported as an optional extension to the Armv8.2-A architecture and newer and are mandatory on Armv8.4-A. The extension can be used by specifying the +dotprod architecture extension. E.g. -march=armv8.2-a+dotprod.
• The Armv8-A +crypto extension has now been split into two extensions for finer grained control:
  • +aes which contains the Armv8-A AES crytographic instructions.
  • +sha2 which contains the Armv8-A SHA2 and SHA1 cryptographic instructions.
  Using +crypto will now enable these two extensions.
• New Armv8.4-A FP16 Floating Point Multiplication Variant instructions have been added. These instructions are mandatory in Armv8.4-A but available as an optional extension to Armv8.2-A and Armv8.3-A. The new extension can be used by specifying the +fp16fml architectural extension on Armv8.2-A and Armv8.3-A. On Armv8.4-A the instructions can be enabled by specifying +fp16.
• New cryptographic instructions have been added as optional extensions to Armv8.2-A and newer. These instructions can be enabled with:
  • +sha3 New SHA3 and SHA2 instructions from Armv8.4-A. This implies +sha2.
  • +sm4 New SM3 and SM4 instructions from Armv8.4-A.
• The Scalable Vector Extension (SVE) is now supported as an optional extension to the Armv8.2-A architecture and newer. This support includes automatic vectorization with SVE instructions, but it does not yet include the SVE Arm C Language Extensions (ACLE). It can be enabled by specifying the +sve architecture extension (for example, -march=armv8.2-a+sve). By default, the generated code works with all vector lengths, but it can be made specific to N-bit vectors using -msve-vector-bits=N.
• Support has been added for the following processors (GCC identifiers in parentheses):
  • Arm Cortex-A75 (cortex-a75).
  • Arm Cortex-A55 (cortex-a55).
  • Arm Cortex-A55/Cortex-A75 DynamIQ big.LITTLE (cortex-a75.cortex-a55).
  The GCC identifiers can be used as arguments to the -mcpu or -mtune options, for example: -mcpu=cortex-a75 or -mtune=cortex-a75 or as arguments to the equivalent target attributes and pragmas.

ARM

• The -mfpu option now takes a new option setting of -mfpu=auto. When set to this the floating-point and SIMD settings are derived from the settings of the -mcpu or -march options. The internal CPU configurations have been updated with information about the permitted floating-point configurations supported. See the user guide for further information about the extended option syntax for controlling architectural extensions via the -march option. -mfpu=auto is now the default setting unless the compiler has been configured with an explicit --with-fpu option.
• The -march and -mcpu options now accept optional extensions to the architecture or CPU option, allowing the user to enable or disable any such extensions supported by that architecture or CPU such as (but not limited to) floating-point and AdvancedSIMD. For example: the option -mcpu=cortex-a53+nofp will generate code for the Cortex-A53 processor with no floating-point support. This, in combination with the new -mfpu=auto option, provides a straightforward way of specifying a valid build target through a single -mcpu or -march option. The -mtune option accepts the same arguments as -mcpu but only the CPU name has an effect on tuning. The architecture extensions do not have any effect. For details of what extensions a particular architecture or CPU option supports please refer to the documentation.
• The -mstructure-size-boundary option has been deprecated and will be removed in a future release.
• The default link behavior for Armv6 and Armv7-R targets has been changed to produce BE8 format when generating big-endian images. A new flag -mbe32 can be used to force the linker to produce legacy BE32 format images. There is no change of behavior for Armv6-M and other Armv7 or later targets: these already defaulted to BE8 format. This change brings GCC into alignment with other compilers for the ARM architecture.
• The Armv8-R architecture is now supported. It can be used by specifying the -march=armv8-r option.
• The Armv8.3-A architecture is now supported. It can be used by specifying the -march=armv8.3-a option.
• The Armv8.4-A architecture is now supported. It can be used by specifying the -march=armv8.4-a option.
• The Dot Product instructions are now supported as an optional extension to the Armv8.2-A architecture and newer and are mandatory on Armv8.4-A. The extension can be used by specifying the +dotprod architecture extension. E.g. -march=armv8.2-a+dotprod.
• Support for setting extensions and architectures using the GCC target pragma and attribute has been added. It can be used by specifying #pragma GCC target ("arch=..."), #pragma GCC target ("+extension"), __attribute__((target("arch=..."))) or __attribute__((target("+extension"))).
• New Armv8.4-A FP16 Floating Point Multiplication Variant instructions have been added. These instructions are mandatory in Armv8.4-A but available as an optional extension to Armv8.2-A and Armv8.3-A. The new extension can be used by specifying the +fp16fml architectural extension on Armv8.2-A and Armv8.3-A. On Armv8.4-A the instructions can be enabled by specifying +fp16.
• Support has been added for the following processors (GCC identifiers in parentheses):
  • Arm Cortex-A75 (cortex-a75).
  • Arm Cortex-A55 (cortex-a55).
  • Arm Cortex-A55/Cortex-A75 DynamIQ big.LITTLE (cortex-a75.cortex-a55).
  • Arm Cortex-R52 for Armv8-R (cortex-r52).
  The GCC identifiers can be used as arguments to the -mcpu or -mtune options, for example: -mcpu=cortex-a75 or -mtune=cortex-r52 or as arguments to the equivalent target attributes and pragmas.

AVR

• The AVR port now supports the following XMEGA-like devices:

  ATtiny212, ATtiny214, ATtiny412, ATtiny414, ATtiny416, ATtiny417, ATtiny814, ATtiny816, ATtiny817, ATtiny1614, ATtiny1616, ATtiny1617, ATtiny3214, ATtiny3216, ATtiny3217

  The new devices are listed under -mmcu=avrxmega3.
  • These devices see flash memory in the RAM address space, so that features like PROGMEM and __flash are not needed any more (as opposed to other AVR families for which read-only data will be located in RAM except special, non-standard features are used to locate and access such data). This requires that the compiler is used with Binutils 2.29 or newer so that read-only data will be located in flash memory.
  • A new command-line option -mshort-calls is supported. This option is used internally for multilib selection of the avrxmega3 variants. It is not an optimization option. Do not set it by hand.
• The compiler now generates efficient interrupt service routine (ISR) prologues and epilogues. This is achieved by using the new AVR pseudo instruction __gcc_isr which is supported and resolved by the GNU assembler.
  • As the __gcc_isr pseudo-instruction will be resolved by the assembler, inline assembly is transparent to the process. This means that when inline assembly uses an instruction like INC that clobbers the condition code, then the assembler will detect this and generate an appropriate ISR prologue / epilogue chunk to save / restore SREG as needed.
  • A new command-line option -mno-gas-isr-prologues disables the generation of the __gcc_isr pseudo instruction. Any non-naked ISR will save and restore SREG, tmp_reg and zero_reg, no matter whether the respective register is clobbered or used.
  • The feature is turned on per default for all optimization levels except for -O0 and -Og. It is explicitly enabled by means of option -mgas-isr-prologues.
  • Support has been added for a new AVR function attribute no_gccisr. It can be used to disable __gcc_isr pseudo instruction generation for individual ISRs.
  • This optimization is only available if GCC is configured with GNU Binutils 2.29 or newer; or at least with a version of Binutils that implements feature PR21683.
• The compiler no more saves / restores registers in main; the effect is the same as if attribute OS_task was specified for main. This optimization can be switched off by the new command-line option -mno-main-is-OS_task.

IA-32/x86-64

• The x86 port now supports the naked function attribute.
• Better tuning for znver1 and Intel Core based CPUs.
• Vectorization cost metrics has been reworked leading to significant improvments on some benchmarks.
• GCC now supports the Intel CPU named Cannonlake through -march=cannonlake. The switch enables the AVX512VBMI, AVX512IFMA and SHA ISA extensions.
• GCC now supports the Intel CPU named and Icelake through -march=icelake. The switch enables the AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID and AVX512VPOPCNTDQ ISA extensions.
• GCC now supports the Intel Control-flow Enforcement Technology (CET) extension through -mibt, -mshstk, -mcet options. One of these options has to accompany the -fcf-protection option to enable code instrumentation for control-flow protection.

NDS32

• New command-line options -mext-perf, -mext-perf2, and -mext-string have been added for performance extension instructions.

Nios II

• The Nios II back end has been improved to generate better-optimized code. Changes include switching to LRA, more accurate cost models, and more compact code for addressing static variables.
• New command-line options -mgprel-sec= and -mr0rel-sec= have been added.
• The stack-smashing protection options are now enabled on Nios II.

PA-RISC

• The default call ABI on 32-bit linux has been changed from callee copies to caller copies. This affects objects larger than eight bytes passed by value. The goal is to improve compatibility with x86 and resolve issues with OpenMP.
• Other PA-RISC targets are unchanged.

PowerPC / PowerPC64 / RS6000

• The PowerPC SPE support is split off to a separate powerpcspe port. See the separate entry for that new port.
• The Paired Single support (as used on some PPC750 CPUs, -mpaired, powerpc*-*-linux*paired*) is deprecated and will be removed in a future release.
• The Xilinx floating point support (-mxilinx-fpu, powerpc-xilinx-eabi*) is deprecated and will be removed in a future release.
• Support for using big-endian AltiVec intrinsics on a little-endian target (-maltivec=be) is deprecated and will be removed in a future release.

PowerPC SPE

Operating Systems

Windows

• GCC on Microsoft Windows can now be configured via --enable-mingw-wildcard or --disable-mingw-wildcard to force a specific behavior for GCC itself with regards to supporting the wildcard character. Prior versions of GCC would follow the configuration of the MinGW runtime. This behavior can still be obtained by not using the above options or by using --enable-mingw-wildcard=platform.

Other significant improvements