## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_LITE_ADDR_WIDTH = 9, DT = INTEGER, BUS = S_AXI_LITE
PARAMETER C_S_AXI_LITE_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI_LITE
PARAMETER C_BASEADDR = 0xffffffff, DT = STD_LOGIC_VECTOR(31 downto 0), PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI_LITE, MIN_SIZE = 0x1000, ASSIGNMENT = REQUIRE, TYPE = NON_HDL
PARAMETER C_HIGHADDR = 0x00000000, DT = STD_LOGIC_VECTOR(31 downto 0), PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI_LITE, ASSIGNMENT = REQUIRE, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_PROTOCOL = AXI4LITE, DT = STRING, BUS = S_AXI_LITE, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_SUPPORTS_READ = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL
PARAMETER C_S_AXI_LITE_SUPPORTS_WRITE = 1, DT = INTEGER, RANGE = (0,1), BUS = S_AXI_LITE, TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_THREADS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_THREAD_ID_WIDTH = 1, DT = integer, RANGE = (1:16), BUS = M_AXI
PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_DATA_WIDTH = 64, DT = integer, RANGE = (32, 64, 128, 256), BUS = M_AXI
PARAMETER C_M_AXI_PROTOCOL = AXI4, DT = string, TYPE = NON_HDL, VALUES = (AXI4 = AXI4, AXI4Lite = AXI4Lite), BUS = M_AXI
# Max number of write commands able to be issued without responses
# In this example, issued writes + unread writes will throttle write address channel
PARAMETER C_INTERCONNECT_M_AXI_WRITE_ISSUING = 8, DT = INTEGER, BUS = M_AXI
#Read Issuing in this example HDL will go as high as write issuing parameter
PARAMETER C_INTERCONNECT_M_AXI_READ_ISSUING = 8, DT = INTEGER, BUS = M_AXI, TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), BUS = M_AXI #,TYPE = NON_HDL
PARAMETER C_M_AXI_SUPPORTS_USER_SIGNALS = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_AWUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_ARUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_WUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_RUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_BUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
PARAMETER C_M_AXI_SUPPORTS_NARROW_BURST = 0, DT = integer, RANGE = (0,1), TYPE = NON_HDL, BUS = M_AXI
# Example Parameters
# Base address of targeted slave
PARAMETER C_M_AXI_TARGET = 0x00000000, DT = std_logic_vector(31 downto 0)
# Burst length for transactions, in C_M_AXI_DATA_WIDTHs
PARAMETER C_M_AXI_BURST_LEN = 16, DT = integer
# Number of address bits to test before wrapping
PARAMETER C_OFFSET_WIDTH = 9, DT = integer
PARAMETER C_DISPLAY_START_ADDRESS = 0x1A000000, DT = std_logic_vector(31 downto 0)
PARAMETER C_M_AXI_RUSER_WIDTH = 1, DT = integer, ISVALID = (C_M_AXI_SUPPORTS_USER_SIGNALS == 1), BUS = M_AXI
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