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[PDF] Submission (382kB)Updated 12 Aug 2015 11:56:20pm EDT · SHA-1 e6ca9d8908de8bc40a6be26dee9c9464a5eb8537

A traditional operating system process consists of a single virtual address space that maps into available physical memory. Virtual memory management was introduced over fifty [more]

A traditional operating system process consists of a single virtual address space that maps into available physical memory. Virtual memory management was introduced over fifty years ago to overcome the scarcity of physical memory by providing an abstraction presenting a larger address space to user processes through virtualization. With the advances of memory and interconnect technology, high-end systems are entering a different world: there is an abundance of physical memory, but a limited number of virtual and physical address bits that prevents directly accessing all the available memory. In this context, mapping available physical address ranges in and out of virtual address spaces becomes a frequent and important operation.

We propose a new operating system design that promotes virtual address spaces to first-class citizens, enabling process threads to attach to, detach from, and switch into multiple virtual address spaces. Our work enables data-centric applications to fully utilize vast physical memory. It optimizes several important use cases, such as leveraging persistent memory, sharing large pointer-based data structures among processes in a workflow, and efficiently accessing very large memory with random patterns.

In this paper, we describe our prototype implementations in the DragonFly BSD and in Barrelfish operating systems. We also present programming semantics and a compiler transformation to ensure safety in pointer-based programming. Finally, we demonstrate the benefits using data-intensive applications. Using the Redis key-value store, GUPS, and SAMTools, we show that our design removes the serialization overhead and improves throughput by 36% over a traditional file-based approach.

I. Hajj, A. Merritt, G. Zellweger, D. Milojicic, W. Hwu, K. Schwan, T. Roscoe, R. Achermann, P. Faraboschi [details]

Izzat El Hajj (University of Illinois at Champaign-Urbana) <elhajj2@illinois.edu>

Alexander Merritt (Georgia Institute of Technology) <merritt.alex@gatech.edu>

Gerd Zellweger (ETH Zürich) <gerd.zellweger@inf.ethz.ch>

Dejan Milojicic (HP Labs) <dejan.milojicic@hp.com>

Wen-Mei Hwu (University of Illinois at Champaign-Urbana) <w-hwu@illinois.edu>

Karsten Schwan (Georgia Institute of Technology) <schwan@cc.gatech.edu>

Timothy Roscoe (ETH Zürich) <troscoe@inf.ethz.ch>

Reto Achermann (ETH Zürich) <acreto@inf.ethz.ch>

Paolo Faraboschi (HP Labs) <paolo.faraboschi@hp.com>

Architecture   Compiler optimizations   Main memory   Memory models   Memory systems   Operating systems   Performance   Programming models and languages   Transactional memory


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Accepted

OveMerRevExpConNovWriQua
Review #36A4234
Review #36B4333
Review #36C2224
Review #36D3324
Review #36E3333

Review #36A

Updated 6 Nov 2015 3:31:13pm EST

Review #36B

Updated 4 Nov 2015 4:12:22pm EST

Review #36D

Updated 4 Nov 2015 3:34:33pm EST

Review #36E

Updated 4 Nov 2015 9:13:51pm EST