Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Processor Core Pipeline
The TM5xxx pipeline is mostly revealed in [4], but here are further notes:
Figure 1 – Crusoe Pipeline Diagram
The top row of the diagram indicates the pipeline for an ALU instruction, with the other rows representing the two other types of logical units. The pipeline is a fairly typical RISC design:
Fetch0: The first 64 bits of a 64-bit or 128-bit bundle are fetched
Fetch1: The second 64 bits are fetched (for 128-bit bundles only)
Regs: Read source registers and decode/disperse instructions>
ALU: Execute single cycle operations in ALU0 and ALU1
Except: Complete two-cycle ALU0/ALU1 ops and detect exceptions
Cache0: Initiate L1 data cache access based on register address
Cache1: Complete L1 data cache access, TLB access and alias checks
Write: Write results back to GPRs or store buffer
Commit: Optionally latch the lower 48 GPRs into the shadow registers
Pages: « Prev 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next »
Discuss (6 comments)