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Detailed Analysis of the TM5800 Microarchitecture and Instruction Set:
CMS Boot Procedure and Memory Map
At power up, the processor begins executing boot code from an internal ROM. After doing basic POST operations, the OEM configuration data (part of the flash ROM) is read via the processor’s 4-pin flash ROM serial interface. This data tells the processor how to configure the system RAM and prepare for copying the main CMS image.
After the on-chip DRAM controller and caches are configured, the main CMS image in flash ROM is streamed into the core, decompressed and copied out to RAM. It will reside at physical address (total system RAM – 16MB). At this point, control is transferred to the main CMS image for further boot.
There are actually two copies of the CMS image in flash ROM. This is a failsafe mechanism: should the first copy fail to boot the processor (for instance, because it was corrupted by a power failure during an update), the second copy, called a “recovery ROM”, is used on the next reboot. It is assumed that if CMS fails to set some internal watchdog register within a few million cycles after bootup, the primary ROM is assumed to be corrupted so the recovery ROM is used.
The decompressed CMS code image is actually mapped to offset 0x8e000 in CMS DRAM space, and takes up around 1.7 MB:
0×00000 to 0x8e000: occupied by CMS loader, etc. (not in CMS image)
0x8e000 to 0x1823f0: 1.0 MB CMS image
0x1823f0 to 0x1b2261: 196 KB CMS data
Above 0x1b2261 (~1.7 MB – 16 MB): uninitialized data, stack, heap and translation cache
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