| Author |
Message |
always@smart
Joined: 08 Feb 2002
Posts: 308
Helped: 7
Location: ASIA
|
 06 Oct 2004 11:09 HSIM verilog simulation? |
|
| tags: hsim manual |
|
|
Hi all,
i've already synthesized the verilog RTL, and i got the netlist in verilog format.
i have the the tech lib in transistor level and i've tried to v2s the netlist to spice (i'm not too sure if i convert it properly or not)
Now, can someone tell me how to simulate verilog/spice netlist and verilog testbench in HSIM? (I've read the HSIM manual, it seems that i need NCverilog to do co-simulation, but i do not have NC-vlog).
Hope someone can help. Thanks in advance.
regards,
smart
|
|
| Back to top |
|
 |
always@smart
Joined: 08 Feb 2002
Posts: 308
Helped: 7
Location: ASIA
|
| 06 Oct 2004 16:38 Re: HSIM verilog simulation? |
|
|
|
|
hi all,
one more thing, what bout the .sdf (standard delay file) how can i add the delay info(sdf) and simulate with netlist(verilog/spice) and testbench(verilog) using HSIM?
hope someone who has done this before can shed me some light...... 
thanks in advnce.
regards,
smart
|
|
| Back to top |
|
|
dumeHCM
Joined: 30 Sep 2004
Posts: 111
Helped: 1
|
| 07 Oct 2004 3:27 Re: HSIM verilog simulation? |
|
|
|
|
| >sdf file is created by extraction tool such as StarRCXT. They are called post layout simulation
|
|
| Back to top |
|
|
always@smart
Joined: 08 Feb 2002
Posts: 308
Helped: 7
Location: ASIA
|
| 07 Oct 2004 5:25 Re: HSIM verilog simulation? |
|
|
|
|
i have already generated the .sdf file from the PnR tool, i wanna know how do i simulate the verilog netlist, and verilog testbench and also adding the .sdf using HSIM? is it possible?
can anyone tell me?
thanks in advnce
regards,
smart
|
|
| Back to top |
|
|
HCM_bucat
Joined: 29 Sep 2004
Posts: 81
Helped: 3
|
| 07 Oct 2004 5:50 Re: HSIM verilog simulation? |
|
|
|
|
| P&R should be the final step of your design. after you get the physical implementation of your design, you want to check if the parasitic R and C of your layout affect much to your design, you should run simulation again with the spdf netlist with hsim or starsimxt. this format is very much lok like hspice format.
|
|
| Back to top |
|
|
troops
Joined: 17 Jan 2003
Posts: 61
|
| 07 Oct 2004 6:43 HSIM verilog simulation? |
|
| tags: verlog simulation |
|
|
vcs and verlog a can do mixed-mode simulation
CAN HSIM do it ???
|
|
| Back to top |
|
|
HCM_bucat
Joined: 29 Sep 2004
Posts: 81
Helped: 3
|
| 07 Oct 2004 16:45 Re: HSIM verilog simulation? |
|
| tags: verlog simulation |
|
|
| troops wrote: |
vcs and verlog a can do mixed-mode simulation
CAN HSIM do it ??? |
Vcs and Verilog can't ! Mixed Mode Simulation is a kind of simulation that can accept Spice netlist and RTL type netlist as Verilog and VHDL.
Yes, Hsim advertise that it can
|
|
| Back to top |
|
|
kermit
Joined: 07 Apr 2002
Posts: 106
Helped: 2
|
| 16 Nov 2004 6:56 Re: HSIM verilog simulation? |
|
| tags: hsim manual |
|
|
Hsim can receive a DSPF/SPEF file as back-annotation file.You can read the manual of hsim ,In ths manual ,you will find a chapter to descripe post layout back annotation.
BTW: In vcsmx and modelsim ,mixed signals indicate verilog and vhdl mixed simulaton,but not digital and analog mixed signal.
But synopsys tools vcs and nanosim can complete analog/digital signal simulation.
I dont know in cadence there is the same platform like synopsys .
|
|
| Back to top |
|
|
moorhuhn
Joined: 10 Jul 2002
Posts: 121
|
| 16 Nov 2004 10:42 Re: HSIM verilog simulation? |
|
| tags: verilog simulation flow hsim manual hsim simulation flow hsimspf |
|
|
It is possible to simulate very large netlists in HSIM, therefore you need not probably do the mixed mode simulation. The flow is:
Translate your Verilog netlist to the transistor one. v2s is ok for it
Include your libraries in the top level circuit.
Example:
.INCLUDE <path_to_your_lib>/scell_lib.spice
.INCLUDE <path_to_your_lib>/your_memory.spice
.
Include your DSPF or SPEF file(s)
.param HSIMSPF=<path_to_your_dspf>/your_file1.dspf
.param HSIMSPF=<path_to_your_dspf>/your_file2.dspf
(you might decide to split the dspf if the size exceeds 2GB)
Include your stimuli obtained from your Verilog simulation
Example:
.param HSIMVECTORFILE=<path_to_your_test_vectors>/test.txt
That is all. Note that simulation including parasitics requires quite a lot of memory.
You should probably use the 64-bit version of the HSIM if you need more than
2.2GB RAM.
The vectors in the tabular format has to be reformatted to the format required by the HSIM. This is somehow described in the Manual. There are options I have used.
signal <list of ports>
radix <spec of groups>
io <input/output def>
mask <input, output other mask def>
period
tskip
;
slope
delay
resistance
logichv
logiclv
;
<cycle_number> <your_vector>
|
|
| Back to top |
|
|
seasonyangd
Joined: 14 Nov 2001
Posts: 80
|
| 17 Nov 2004 6:51 HSIM verilog simulation? |
|
| tags: cosim hsim hsim cosim |
|
|
| You can refer to cosim note in HSIM doc dir. This file described the cosim method verilog/spice netlist.
|
|
| Back to top |
|
|
always@smart
Joined: 08 Feb 2002
Posts: 308
Helped: 7
Location: ASIA
|
| 19 Nov 2004 10:46 Re: HSIM verilog simulation? |
|
|
|
|
| moorhuhn wrote: |
Include your stimuli obtained from your Verilog simulation
Example:
.param HSIMVECTORFILE=<path_to_your_test_vectors>/test.txt
|
hi moorhuhn,
can you tell me how do u actually convert the verilog testbench to spice? i've tried to use "v2s" to convert, but i got error too many errors, for ex:
1. #100 for delay
2. a= 1 assignment
3. pulse_task(a, b) task
any advice?
thanks in advance
regards,
smart
|
|
| Back to top |
|
|
kermit
Joined: 07 Apr 2002
Posts: 106
Helped: 2
|
| 19 Nov 2004 11:19 Re: HSIM verilog simulation? |
|
|
|
|
v2s tool is used to convert your synthesised netlist to spice model for simulation,
not your top RTL testbech.
you can use $fdisplay to write the stimuli vector.such as :
| Quote: |
;
signal XCVR_SELECT TERM_SELECT OPMODE[1-0] TX_VALID TX_VALIDH DATA_IN[15-0] VCONTROL_LOADM VCONTROL[3-0] TxBitstuffEnable TxBitstuffEnableH IdPullup ID DpPulldown DmPulldown Tx_Enable_N Tx_DAT Tx_SE0 FsLsSerialMode LS_ENABLE DP DM
radix 1 1 2 1 1 4444 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1
io i i i i i iiii i i i i i i i i i i i i i u u
vih 1.8V
vih 3.3V 0000 0000 0000 0000 0000 0011
vil 0V
vhth 1.2V
vlth 0.5V
slope 1000ps
delay 3000ns
tunit 1ps
2 0 0 0 0 0 xx00 1 x 1 1 z z 0 0 1 1 0 0 0 x x
83200 1 1 0 0 0 xx00 1 x 1 1 z z 0 0 1 1 0 0 0 x x
83304 1 1 0 0 0 0000 1 0 1 1 z z 0 0 1 1 0 0 0 x x
|
The detailed information about digital vector file pls read the manual "Digital Vector File"
|
|
| Back to top |
|
|