( ESNUG 434 Item 7 ) -------------------------------------------- [11/18/04]

From: Claudia Relyea <claudia_relyea=user domain=mentor spot calm>
Subject: Get Calibre-xRC Hierarchical Parasitic Netlists Into Nassda HSIM

Hi John, 

I thought your readers might be interested in the steps required to take
Calibre-xRC hierarchical parasitic netlist output into Nassda HSIM.

I've seen a significant proportion of Calibre xRC users have been using 
Nassda's hierarchical circuit simulation tools (LEXSIM or HSIMplus) to 
perform post-layout verification and analysis.  Two of the nanometer
effects they face are

    1) delay and functional noise induced by a large number of coupling
       capacitors in adjacent signal lines,
and
    2) dynamic voltage drop analysis, and its impact on circuit performance
       (for instance, degradation of memory access time, or push out of
       timing constraints due to voltage drop). 

Software required: Calibre xRC 2004.1 and Nassda HSIM v5.0, including the
appropriate HSIMplus option(s) for post-layout analysis (PWRA for power net
voltage drop and reliability analysis; PLX for post-layout acceleration 
including coupling capacitors, etc.) 

Steps involved in the flow: 

     a.) Hierarchical LVS comparison 

            calibre -lvs -hier -hcell <hcell list> \
                    -spice <layout netlist> <SVRF rule file> 

     b.) Hierarchical parasitic extraction 

            calibre -xrc -rc/rcc -full  \
                    -select -xcell <xcell list> <SVRF rule file> 

     c.) Hierarchical netlisting 

            calibre -xrc -full -xcell <xcell list> <SVRF rule file> 

     d.) Hierarchical simulation 

            hsim <simulation netlist file> 

First run Calibre LVS hierarchically to extract a hierarchical layout
netlist and the source space correlation.  Then run Calibre-xRC to generate
a hierarchical DSPF netlist.  Finally, use HSIM to backannotate this to the
hierarchical source schematic netlist.

  PEX NETLIST DISTRIBUTED <netlist name> \ 
             DSPF 1e-6 SOURCE RLOCATION RWIDTH RLAYER UNIT LENGTH

In addition, the following environment variables must be set: 

  PEX_FMT_EXPORT_NET_PORT ON 
  PEX_FMT_HP_PORT_MAP_MODE "TEMPLATE CELLNAME SOURCE" 
  PEX_NASSDA ON 

If the pre-layout simulation hierarchy is preserved, the extracted device 
parameters and parasitic nets can be back-annotated by HSIMplus to the 
hierarchical source or pre-layout netlist (specified as "prelayout.sp" 
below).  The HSIM parameter HSIMDPF defines the DPF file for device 
parameter back-annotation. 
  
The parameter HSIMSPF defines the DSPF file for back-annotation of
parasitic RCs.  In the Calibre-xRC/HSIM flow, the device parameters as
well as the parasitic RCs are back-annotated from the same xRC output
netlist, so both HSIMSPF and HSIMDPF should point to the xRC DSPF netlist.

For signal net analysis of RC or RCC netlists, the following HSIM
parameters should be used: 

        .param HSIMSPF = "xrc.dist.dspf" 
        .param HSIMSPFFDELIM = '__' 
        .param HSIMSPFMULTISUB = 1 
        .param HSIMSPFMSGLEVEL = 3 
        .param HSIMDPF = "xrc.dist.dspf" 
        .param HSIMDPFPFX = 'M' 
        .param HSIMDPFHIERID = '/' 
        .param HSIMDPFSFX = '__' 
        .param HSIMDPFSCALE = 1u 
        .param HSIMPOSTL = 1 
        .param HSIMSPFPLX = 1 
        .inc "prelayout.sp" 

For signal net electro-migration analysis, the following HSIM parameters 
should be used in addition to those listed above:

        .param HSIMSPFFEEDTHRU = 1 
        .param HSIMRANET = "<list of signal nets>" 
        .param HSIMRATAU = 1n 
        .param HSIMRATCL = "tcl file for reliability analysis" 
        .param HSIMSIGRA = 1 

For hierarchical power net dynamic voltage drop analysis, use the following 
HSIM parameters, in conjunction with the HSIM parameters listed
above (carefully selecting the parameters used to enable and control the
specific analysis task being undertaken):

        .param HSIMPWNAME = "VDD VSS VSSA" 
        .param HSIMSPFPWNET = 4 
        .param HSIMRATAU = 1n 
        .param HSIMRATCL = "tcl file for reliability analysis" 
        .param HSIMSPFFEEDTHRU = 1 
        .param HSIMSPFPWFLAT = 1 
        .param HSIMSPFPOS = "block_position.file" 
        .param HSIMSPFPLX = 1 
        .param HSIMPWRA = 1 


Flow Recommendations:

I recommend that xcells be chosen with some care for hierarchical
extraction.  This will benefit the overall accuracy of the extraction
results, since coupling capacitance is extracted but lumped to ground
between hierarchical boundaries.  Typically, xcells are selected according
to the pre-layout simulation hierarchy.  Put cells containing hierarchical
nodes in the xcell list to preserve them for debug.  In order to maximize
hierarchical capacitance extraction accuracy, a memory bit-cell is usually
not a suitable xcell if its geometries overlap with those in neighboring
bit-cells, shares device layers with other adjacent cells, or is not
DRC/LVS clean by itself.  Instead, a minimum size array of memory bit-cells
(e.g. 2x2, or 8x8) should be selected.

    - Claudia Relyea
      Mentor Graphics                            Wilsonville, OR