James A. Kahle IBM Systems and Technology Group, STI Design Center, 11400 Burnet Road, Austin, Texas 78758 (jakahle@us.ibm.com). Mr. Kahle is an IBM Fellow; his current title is Director of Technology for the Austin-based STI Design Center for Cell technology. This is a partnership with IBM, Sony, and Toshiba. Mr. Kahle received his B.S. degree from Rice University in 1983. He has been working for IBM since the early 1980s on RISC-based microprocessors. His work started in physical design tools and is currently concentrated on RISC architecture. Mr. Kahle was a key designer for the RIOS I processor, which launched IBM into the RS/6000* line of workstations and servers. He was also one of the founding members of the Somerset Design Center, where he was the project manager for the PowerPC 603* and follow-on processors which led to the PowerPC G3. He was key to the definition of the PowerPC architecture and of the superscalar techniques used at IBM, and has been at the forefront of superscalar design and multiscalar and SMT microarchitectures. Mr. Kahle was the Chief Architect for the POWER4* core, and assists in PowerPC roadmap planning.

Michael N. Day IBM Systems and Technology Group, STI Design Center, 11400 Burnet Road, Austin, Texas 78758 (mnday@us.ibm.com). Mr. Day received a B.S. degree in electrical engineering–computer science from the University of Texas at Austin in 1977. He joined IBM that same year as an engineer designing and implementing hardware and software for a large multi-user timesharing office product system that included workstation controllers, full page displays, speech digitization, and filing systems. He then became the lead firmware and software architect for the first IBM battery-powered laptop computer with advanced power-management features. In 1987 he became a kernel subsystem architect on the premier IBM UNIX OS project called AIX*. Mr. Day was elected to the IBM Academy of Technology in 1992, and he went on to become chief architect of AIXv4, delivering SMP support and kernel-based threads. In 1997 he became an IBM Distinguished Engineer. The following year he led a real-time broadband video streaming project introducing the MediaStreamer* product based on AIX. He subsequently worked on the design and implementation of AIX on IA64, then moved to the STI project in 2001 as Chief System Software Architect, defining the programming features of the Cell processor, enabling Linux and software tool chains to support various programming models for the Cell processor. He also leads a team of programmers developing application libraries, test suites, workloads, and demonstration programs for the Cell processor.

H. Peter Hofstee IBM Systems and Technology Group, STI Design Center, 11400 Burnet Road, Austin, Texas 78758 (hofstee@us.ibm.com). Dr. Hofstee received his doctorandus degree in theoretical physics from the Rijks Universiteit Groningen, The Netherlands, in 1988, and his M.S. and Ph.D. degrees in computer science from the California Institute of Technology in 1991 and 1994, respectively. After two years on the faculty at Caltech, in 1996 he joined the IBM Austin Research Laboratory, where he participated in the design of two 1-GHz PowerPC prototypes, focusing on microarchitecture, logic design, and chip integration. In 2000 he helped start the Sony–Toshiba–IBM Design Center to design a next generation of processors for the broadband era, code-named “Cell.” Dr. Hofstee is a member of the Cell architecture team and the chief architect of the synergistic processor in Cell. He was elected to the IBM Academy of Technology in 2004.

Charles R. Johns IBM Systems and Technology Group, STI Design Center, 11400 Burnet Road, Austin, Texas 78758 (crjohns@us.ibm.com). Mr. Johns is a Senior Technical Staff Member in the Sony/Toshiba/IBM Design Center. He received his B.S. degree in electrical engineering from the University of Texas at Austin in 1984. After joining IBM at Austin that same year, he worked on various disk, memory, voice communication, and graphics adapters for the IBM Personal Computer. From 1988 until he moved to the STI project in 2000, he was part of the Graphics Organization and was responsible for the architecture and development of entry-level and mid-range 3D graphics adapters and rater engines. Mr. Johns is now responsible for Broadband Processor Architecture (BPA) and participates in the development of the Broadband Engine (the first implementation of the BPA).

Theodore R. (Ted) Maeurer IBM Systems and Technology Group, STI Design Center, 11400 Burnet Road, Austin, Texas 78758 (maeurer@us.ibm.com). Mr. Maeurer is manager of the software organization for the Austin-based STI Design Center. He received his B.S. and M.S. degrees in computer science from Rensselaer Polytechnic Institute in 1988 and 1989, respectively, and his M.S. degree in engineering and management from the Massachusetts Institute of Technology in 1999. Mr. Maeurer began his career at IBM in 1990 working on operating systems for IBM high-end servers during the transition from bipolar to highly clustered CMOS-based systems. He later worked on object-based middleware technologies as part of the first activities at IBM to commercialize this technology for high-end systems. In 2001 Mr. Maeurer joined the STI Design Center, where he has been a member of the management team. In this role he has been responsible for the development of software technologies for the Cell processor.

David Shippy IBM Systems and Technology Group, STI Design Center, 11400 Burnet Road, Austin, Texas 78758 (shippy@us.ibm.com). Mr. Shippy received a B.S. degree in electrical engineering from the University of Kentucky in 1983 and an M.S. degree in computer engineering from Syracuse University in 1987. He has been involved with the design of high-performance processors for more than 20 years, working on processors from notebooks to game machines to mainframes. He was one of the lead architects for the POWER2*, G3 PowerPC, and POWER4* processor designs. He is currently the chief architect for the power processing unit for the Cell processor. Mr. Shippy holds numerous patents, has received an IBM Tenth Plateau Invention Achievement Award, and has been recognized as an IBM Master Inventor. He is an expert in the area of high-performance processor architecture and design.

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