Success Stories
GSIM success stories in customer evaluations
Post-layout oscillator
Circuit has half a million device elements. Traditional Spice
simulators have no hope in simulating the circuit. A new
analog simulator that claims to be 5-10x faster would take
1000 days to finish the transient simulation. It only took GSIM
11 days to run the simulation.
Full-chip transceiver
Circuit has 1.3 million transistors and 1 million RC's. Again
traditional Spice simulators have no hope in simulating the
circuit. The new analog simulator that claims to be 5-10x
faster took 6 days to finish the simulation. It only took GSIM
1.5 days to run the simulation.
A traditional FastMOS or timing simulator had accuracy
problem with the simulation. It couldn't even get the circuit
functionality right.
Post-layout memory chip
GSIM was able to simulate post-layout memory chip with 2
million transistors and 9 million RC's.
GSIM is the largest-capacity Spice simulator in the world.
Sigma-Delta ADC
Circuit has 71k device elements including 17k transistors. It
took Gsim only 28.24 hours to simulate 1037144 timesteps
where the transient stop time is 63us.
Filter
Circuit has 1k transistors. A golden Spice simulator took 40+
hours to run the transient simulation. A new analog simulator
that claims to be 5-10x faster was indeed 10x faster. Gsim
was 10x faster also. However, the new analog simulator was
too aggressive in timestep control. The number of timesteps
it took was only half of the number of timesteps Gsim took.
Certainly its result is not as accurate as Gsim's. It can't
resolve signal overshoots as well as Gsim can.