ユニデン地上デジタルチューナー DT100-HDMIを分解してみた

PARTS

• Single chip STB decoder (MULTI2 descramble, MPEG-2 decoder, audio dac, video encoder, HDMI tx): ST STi7710 pdf block
• 256Mb DDR SDRAM x2 : winbond W9425G6CH-5
• 32Mb Flash : SST SST39VF3201 pdf
• Tuner Module : MITSUMI DVT33-J04DT pdf
  • demodulator : TOSHIBA TC90A87XBG pdf
  • synthsizer : PHILIPS TDA6651TT pdf
• 2ch Opamp(for audio) : JRC NJM2737 pdf

PHOTOS

I2C LOG

• ch2_ch1.txt
• set frequency of sythesizer to UHF 27ch.

    8.748mS: 18 W FE C2 10 CA C1 A8 82   . . . . . . 
  
  FE : start byte?
  C2 : address byte ( 1 1 0 0    0 MA1 MA2 R/~W= C2 refer to Table5 in detasheet)
  10 : Divider byte 1 ( 0 N14 N13 N12 N11 N10 Nn9 N8)
  CA : Divider byte 2 ( N7 N6 N5 N4 N3 N2 N2 N1 N0)  N = 0x10CA = 4298 
  C1 : Control byte 1 ( 1  T/A=1 T2 T1 T0 R2 R1 R0)  Frequency Step = 142.98KHz = (1/7)
  A8 : Control byte 2 ( CP2 CP1 CP0 BS5 BS4 BS3 BS2 BS1)
  82 : Control Byte 1 ( 1  T/A=0 0 0 ATC AL2 AL1 AL0)  
  
  target freqquecy  UHF 27ch = 557.142857 MHz,  IF = 57 MHz
  N=557.142857+57=614.142857/(1/7)=4299 
  
  thanks to 148 (2ch)
  

• set frequency of sythesizer to UHF 26ch.

    22.056mS: 18 W FE C2 10 A0 C1 A8 82   . . . . . . 
  

serial TS out

• RS6 (CLK down edge), RS1 (Data), PBVAL, SBYTE
• SYNC BYTE 0100 0111 -> 0x47
  
• logiana_uniden.zip by http://optimize.ath.cx/cusb/logiana.html

serial to pararell converter

module top(SCLK, SDATA, SBYTE, PBVAL, PDATA, PSBYTE);
	input SCLK;
	input SDATA;
	input SBYTE;
	input PBVAL;
	 
	output[7:0] PDATA;
	output PSBYTE;

	reg[2:0] count;
	reg[7:0] sreg;
	reg[7:0] dout;
	reg sbyte_reg;
	reg sbyte_out;

	always@(negedge SCLK)
	begin
	 
		if(PBVAL==0)				//RESET
		begin
			count<=3'b000;
			dout<=8'b00000000;
			sreg<=8'b00000000;
			sbyte_reg<=0;
			sbyte_out<=0;
		end
		else							//set shift register
		begin
			sreg[0]<=SDATA;
			sreg[1]<=sreg[0];
			sreg[2]<=sreg[1];
			sreg[3]<=sreg[2];
			sreg[4]<=sreg[3];
			sreg[5]<=sreg[4];
			sreg[6]<=sreg[5];
			sreg[7]<=sreg[6];	
			
			count <= count +1;
			
			sbyte_reg <= SBYTE;
		end 
		
		if(count[2:0]==0)			//set shift register to output 
		begin
			dout[7:0]<=sreg[7:0];
			sbyte_out<=sbyte_reg;
		end	
	 end
	 	 
	 
	 assign PDATA[7:0]=dout[7:0];
	 assign PSBYTE=sbyte_out;
	 
endmodule